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Interrupt Controller Modules
17.3.2
Prioritization Between Interrupt Controllers
The interrupt controllers have a fixed priority, where INTC0 has the highest priority, and INTC1 has the
lowest priority. If both interrupt controllers have active interrupts at the same level, then the INTC0
interrupt is serviced first. If INTC1 has an active interrupt with a higher level than the highest INTC0
interrupt, then the INTC1 interrupt is serviced first.
17.3.3
Low-Power Wake-up Operation
The system control module (SCM) contains an 8-bit low-power control register (LPCR) to control the
low-power stop mode. This register must be explicitly programmed by software to enter low-power mode.
It also contains a wake-up control register (WCR) sets the priority level of the interrupt necessary to bring
the device out of the specified low-power mode. Refer to
of the LPCR and WCR registers, as well as more information on low-power modes.
Each interrupt controller provides a special combinatorial logic path to provide a special wake-up signal
to exit from the low-power stop mode. This special mode of operation works as follows:
1. The WCR register is programmed, setting the ENBWCR bit and the desired interrupt priority level.
2. At the appropriate time, the processor executes the privileged STOP instruction. After the
processor has stopped execution, it asserts a specific processor status (PST) encoding. Issuing the
STOP instruction when the WCR[ENBWCR] bit is set causes the SCM to enter the mode specified
in LPCR[LPMD].
3. The entry into a low-power mode is processed by the low-power mode control logic, and the
appropriate clocks (usually those related to the high-speed processor core) are disabled.
4. After entering the low-power mode, the interrupt controller enables a combinational logic path
which evaluates any unmasked interrupt requests. The device waits for an event to generate a level
7 interrupt request or an interrupt request with a priority level greater than the value programmed
in WCR[PRILVL].
5. After an appropriately high interrupt request level arrives, the interrupt controller signals its
presence, and the SCM responds by asserting the request to exit low-power mode.
6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks.
7. With the processor clocks enabled, the core processes the pending interrupt request.
For more information, see
17.4
Initialization/Application Information
The interrupt controller's reset state has all requests masked via the IMR. Before any interrupt requests are
enabled, the following steps must be taken:
1. Set the ICONFIG register to the desired system configuration.
2. Program the ICRn registers with the appropriate interrupt levels.
3. The reset value for the level mask registers (CLMASK and SLMASK) is 0xF (no levels masked).
Typically, these registers do not need to be modified before interrupts are enabled.
4. Load the appropriate interrupt vector tables and interrupt service routines into memory.
17-18
Section 9.2.1, "Wake-up Control Register (WCR)".
Chapter 9, "Power Management,"
for definitions
Freescale Semiconductor
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