Freescale Semiconductor MCF54455 Reference Manual page 249

Universal Serial Bus Interface – On-The-Go Module
Field
31–20 Reserved, must be cleared.
19–16 Prime endpoint transmit buffer. For each endpoint, a corresponding bit requests that a buffer be prepared for a
PETB transmit operation to respond to a USB IN/INTERRUPT transaction. Software must write a 1 to the corresponding
bit when posting a new transfer descriptor to an endpoint. Hardware automatically uses this bit to begin parsing for
a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware clears this bit when
associated endpoint(s) is (are) successfully primed.
Note: These bits are momentarily set by hardware during hardware re-priming operations when a dTD retires, and
the dQH updates.
15–4 Reserved, must be cleared.
3–0 Prime endpoint receive buffer. For each endpoint, a corresponding bit requests that a buffer be prepared for a
PERB receive operation to respond to a USB OUT transaction. Software must write a 1 to the corresponding bit when
posting a new transfer descriptor to an endpoint. Hardware automatically uses this bit to begin parsing for a new
transfer descriptor from the queue head and prepare a receive buffer. Hardware clears this bit when associated
endpoint(s) is (are) successfully primed.
Note: These bits are momentarily set by hardware during hardware re-priming operations when a dTD retires, and
the dQH updates.
10.3.4.19 Endpoint Flush Register (EPFLUSH)
This register is not defined in the EHCI specification. This register used only in device mode.
Address: 0xFC0B_01B4 (EPFLUSH)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–20 Reserved, must be cleared.
19–16 Flush endpoint transmit buffer. Writing a 1 to a bit in this field causes the associated endpoint to clear any primed
FETB buffers. If a packet is in progress for an associated endpoint, that transfer continues until completion. Hardware
clears this register after the endpoint flush operation is successful.
15–4 Reserved, must be cleared.
3–0 Flush endpoint receive buffer. Writing a 1 to a bit in this field causes the associated endpoint to clear any primed
FERB buffers. If a packet is in progress for an associated endpoint, that transfer continues until completion. Hardware
clears this register after the endpoint flush operation is successful. FERB[3] corresponds to endpoint 3.
10.3.4.20 Endpoint Status Register (EPSR)
This register is not defined in the EHCI specification. This register is only used in device mode.
10-42
Table 10-37. EPPRIME Field Descriptions
FETB
Figure 10-35. Endpoint Flush Register (EPFLUSH)
Table 10-38. EPFLUSH Field Descriptions
Description
9
0 0 0 0 0 0 0 0 0 0 0 0
Description
Access: User read/write
8 7 6 5 4 3 2 1 0
FERB
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