Freescale Semiconductor MCF54455 Reference Manual page 585

Advanced Technology Attachment (ATA)
• DMA request. Bit 7 of the interrupt registers control ATA DMA request. If the DMA bit is set in
the ATA_IER and ATA_ISR registers, a request is sent to the DMA controller. The goal of this
request is to inform the DMA that running data transfer has ended.
These three interrupt registers have mostly the same bits. If a bit is set in the ATA_ISR register, its interrupt
is pending and produces an interrupt if the corresponding bit is set in the ATA_IER register. Some bits in
the ATA_ISR are sticky bits. Writing a 1 to the corresponding bit in the interrupt clear register (ATA_ICR)
resets them.
23.3.6.1 Interrupt Status Register (ATA_ISR)
The interrupt status register reports the status of various conditions of the ATA controller and its FIFO.
Address: 0x9000_0028 (ATA_ISR)
7
R DMA
W
1
Reset 0
1
Bits DMA and INT only reset to 0 if during reset the interrupt input is low.
Field
7 ATA DMA request. Reflects the value of the ATA_INTRQ interrupt input signal. When this bit is set in the
DMA ATA_ISR and ATA_IER registers, the DMA end-of-transfer request is sent. The interrupt clear register, ATA_ICR,
has no influence on this bit.
0 ATA_INTRQ negated
1 ATA_INTRQ asserted
6 FIFO underfow. Sticky bit that reports FIFO underflow. It is cleared by writing a 1 to this bit in the ATA_ICR
FUF register. When this bit is set in the ATA_ISR and ATA_IER registers, an interrupt is requested to the CPU.
0 No FIFO underflow
1 FIFO underflow detected
5 FIFO overflow. Sticky bit that reports FIFO overflow. It is cleared by writing a 1 to this bit in the ATA_ICR register.
FOF When this bit is set in the ATA_ISR and ATA_IER registers, an interrupt is requested to the CPU.
0 No FIFO overflow
1 FIFO overflow detected
4 Controller idle. Indicates the ATA protocol engine is idle (there is no activity on the ATA bus). When the bit is set
IDLE in the ATA_ISR and ATA_IER registers, an interrupt is requested to the CPU. The ATA_ICR register has no
influence on this bit.
0 Activity on the ATA bus
1 No activity on the ATA bus, engine is idle
23-10
6 5
FUF FOF IDLE
0 0
Figure 23-7. Interrupt Status Register (ATA_ISR)
Table 23-5. ATA_ISR Field Descriptions
4 3 2
INT
1
1 0 —
Description
Access: User read-only
1 0
— —
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