1. Manuals
  2. Brands
  3. Freescale Semiconductor Manuals
  4. Computer Hardware
  5. MC68HC908MR16
  6. Datasheet

Freescale Semiconductor MC68HC908MR16 Datasheet

Freescale semiconductor microcontrollers data sheet
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
MC68HC908MR32
MC68HC908MR16
Data Sheet
M68HC08
Microcontrollers
MC68HC908MR32
Rev. 6.1
07/2005
freescale.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the MC68HC908MR16 and is the answer not in the manual?

Questions and answers

Related Manuals for Freescale Semiconductor MC68HC908MR16

Summary of Contents for Freescale Semiconductor MC68HC908MR16

  • Page 1 MC68HC908MR32 MC68HC908MR16 Data Sheet M68HC08 Microcontrollers MC68HC908MR32 Rev. 6.1 07/2005 freescale.com...
  • Page 3 Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved.

  • Page 4: Revision History

    Figure 2-1. MC68HC908MR32 Memory Map — Added FLASH Block Protect Register (FLBPR) at address location $FF7E August, 2001 Figure A-1. MC68HC908MR16 Memory Map — Added FLASH Block Protect Register (FLBPR) at address location $FF7E October, 3.3.3 Conversion Time — Reworked equations and text for clarity.

  • Page 5: Table Of Contents

    Appendix A MC68HC908MR16 ........
  • Page 6 List of Chapters MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...
  • Page 7 FLASH Block Protect Register ..........43 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1...
  • Page 8 CGM External Connections ..........63 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1...
  • Page 9 Stop Mode ..............77 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ) .
  • Page 10 Stop Mode ..............100 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1...
  • Page 11 Manual Mode ............140 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1...
  • Page 12 SCI Control Register 2 ........... 171 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1...
  • Page 13 Transmission Formats ............199 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1...
  • Page 14 TIMA Channel Registers ..........232 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1...
  • Page 15 Break Flag Control Register ..........255 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1...
  • Page 16 56-Pin Shrink Dual In-Line Package (SDIP) ........277 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1...

  • Page 17: Chapter 1 General Description

    (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. The information contained in this document pertains to the MC68HC908MR16 with the exceptions shown Appendix A MC68HC908MR16.

  • Page 18: Mcu Block Diagram

    • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908MR32. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...
  • Page 19 M68HC08 CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE CGMXFC SYSTEM INTEGRATION MODULE MODULE...

  • Page 20: Pin Assignments

    PTB7/ATD7 PTC0/ATD8 PTC1/ATD9 DDAD SSAD REFL REFH PTC2 PTC3 PTC4 PTC5 Figure 1-2. 64-Pin QFP Pin Assignments MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Figure 1-3 shows the 56-pin SDIP pin PTF5/TxD PTF4/RxD PTF3/MISO PTF2/MOSI PTF1/SS PTF0/SPSCK PTE7/TCH3A PTE6/TCH2A PTE5/TCH1A...
  • Page 21 PTD1/FAULT2 PTD2/FAULT3 PTD3/FAULT4 PTD4/IS1 Note: PTC1, PTE0, PTE1, PTE2, PTF0, PTF1, PTF2, and PTF3 are removed from this package. Figure 1-3. 56-Pin SDIP Pin Assignments MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PTA2 PTA3 PTA4 PTA5 PTA6 PTA7...

  • Page 22: Power Supply Pins (Vdd And Vss )

    (CGM). SSAD Decoupling of these pins should be per the digital supply. See MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 and V 0.1 µF 1–10 µF Figure 1-4.

  • Page 23: External Filter Capacitor Pin (Cgmxfc)

    1.4.14 PWM Pins (PWM6–PWM1) PWM6–PWM1 are dedicated pins used for the outputs of the pulse-width modulator module (PWMMC). These are high-current sink pins. See Chapter 19 Electrical Specifications. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor and V DDAD SSAD...

  • Page 24: Pwm Ground Pin (Pwmgnd)

    (SCI) and four of its pins with the serial peripheral interface module (SPI). See Chapter 15 Serial Peripheral Interface Module (SPI), Chapter 13 Serial Communications Interface Module (SCI), and Chapter 10 Input/Output (I/O) Ports (PORTS). MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 25: Chapter 2 Memory

    Some I/O bits are reserved. Writing to a reserved bit can have unpredictable effects on MCU operation. In register figures, reserved bits are marked with the letter R. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor (Figure...

  • Page 26: I/O Section

    Figure 2-1 shows the memory map for the MC68HC908MR32 while the memory map for the MC68HC908MR16 is shown in MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Figure 2-2, contain most of the control, status, and data registers. Appendix A MC68HC908MR16...
  • Page 27 ↓ $FFD1 $FFD2 ↓ $FFFF Figure 2-1. MC68HC908MR32 Memory Map MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor I/O REGISTERS — 96 BYTES RAM — 768 BYTES UNIMPLEMENTED — 31,904 BYTES FLASH — 32,256 BYTES SIM BREAK STATUS REGISTER (SBSR)
  • Page 28 Data Direction Register F $000D (DDRF) See page 110. U = Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet 1 of 8) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 7 Read: PTA7 PTA6 PTA5 Write:...
  • Page 29 TIMA Channel 2 Status/Control $0019 Register (TASC2) See page 229. U = Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet 2 of 8) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Bit 7 Read: TOIE TSTOP Write:...
  • Page 30 $0025 (PWMOUT) See page 154. U = Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet 3 of 8) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 7 Read: Bit 15 Bit 14 Bit 13 Write:...
  • Page 31 PWM 4 Value Register Low $0031 (PVAL4L) See page 145. U = Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet 4 of 8) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Bit 7 Read: Write: Reset: Read:...
  • Page 32 $003D (SCDR) See page 177. U = Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet 5 of 8) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 7 Read: Bit 15 Bit 14 Bit 13 Write:...
  • Page 33 TIMB Counter Register High $0052 (TBCNTH) See page 246. U = Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet 6 of 8) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Bit 7 Read: SCP1 Write: Reset:...
  • Page 34 See page 68. $005F Unimplemented U = Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet 7 of 8) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 7 Read: Bit 7 Bit 6 Bit 5 Write:...
  • Page 35 COP Control Register $FFFF (COPCTL) See page 77. U = Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet 8 of 8) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Bit 7 Read: Write: Reset: Read:...
  • Page 36 Memory Table 2-1 is a list of vector locations. 1. The SPI module is not available in the 56-pin SDIP package. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Table 2-1. Vector Addresses Address $FFD2 SCI transmit vector (high) $FFD3 SCI transmit vector (low)

  • Page 37: Monitor Rom

    Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the contents of the CPU registers. For M68HC05 and M1468HC05 compatibility, the H register is not stacked. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Address...

  • Page 38: Flash Memory (Flash)

    = Unimplemented Figure 2-3. FLASH Control Register (FLCR) 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE NOTE NOTE...

  • Page 39: Flash Page Erase Operation

    FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 40: Flash Mass Erase Operation

    1. When in monitor mode, with security sequence failed (see of any FLASH address. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 within the FLASH memory address range. NOTE NOTE 18.3.2...

  • Page 41: Flash Program Operation

    Characteristics. 1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, t MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE...
  • Page 42 This row program algorithm assumes the row/s to be programmed are initially erased. Figure 2-4. FLASH Programming Flowchart MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 SET PGM BIT READ THE FLASH BLOCK PROTECT REGISTER WRITE ANY DATA TO ANY FLASH ADDRESS...

  • Page 43: Flash Block Protection

    The FLASH is protected from this start address to the end of FLASH memory at $FFFF. With this mechanism, the protect start address can be XX00 and XX80 (128 bytes page boundaries) within the FLASH memory. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE Register.

  • Page 44: Wait Mode

    Standby mode is the power-saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is at a minimum. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 16-BIT MEMORY ADDRESS FLBPR VALUE Start of Address of Protect Range The entire FLASH memory is protected.

  • Page 45: Chapter 3 Analog-To-Digital Converter (Adc)

    When the conversion is completed, the ADC places the result in the ADC data register (ADRH and ADRL) and sets a flag or generates an interrupt. See MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure...
  • Page 46 M68HC08 CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE CGMXFC SYSTEM INTEGRATION MODULE MODULE...

  • Page 47: Adc Port I/O Pins

    All other input voltages will result in $3FF if greater than V if less than V REFL Input voltage should not exceed the analog supply voltages. See 19.13 Analog-to-Digital Converter (ADC) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ADC DATA REGISTERS ADC VOLTAGE IN ADVIN...

  • Page 48: Conversion Time

    Left justification will place the eight most significant bits (MSB) in the corresponding ADC data register high, ADRH. This may be useful if the result is to be treated as an 8-bit result where the two least MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 16 to17 ADC Cycles...

  • Page 49: Monotonicity

    RESULT RESULT IDEAL 10-BIT CHARACTERISTIC WITH QUANTIZATION = ±1/2 3.3.6 Monotonicity The conversion process is monotonic and has no missing codes. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE Figure 3-3. IDEAL 8-BIT CHARACTERISTIC WITH QUANTIZATION = ±1/2...

  • Page 50: Interrupts

    ADC. Connect the V REFL . A finite current will be associated with V SSAD In the 56-pin shrink dual in-line package (SDIP), V together. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 DDAD as its power pin. Connect the V DDAD NOTE SSAD as its ground pin.

  • Page 51: Adc Voltage In (Advin)

    These I/O registers control and monitor operation of the ADC: • ADC status and control register, ADSCR • ADC data registers, ADRH and ARDL • ADC clock register, ADCLK MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor and V REFH and V REFH REFL...

  • Page 52: Adc Status And Control Register

    The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for reduced power consumption for the MCU when the ADC is not used. Recovery from the disabled state requires one conversion cycle to stabilize. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 AIEN ADCO...
  • Page 53 1. ATD9 is not available in the 56-pin SDIP package. 2. Used for factory testing. 3. If any unused channels are selected, the resulting ADC conversion will be unknown. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Table 3-1. Mux Channel Select...

  • Page 54: Adc Data Register High

    ADC conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. Until ADRL is read, all subsequent ADC results will be lost. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Unaffected by reset = Reserved...

  • Page 55: Adc Clock Register

    ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 3-2 ADIV2 X = don’t care MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Unaffected by reset = Reserved Unaffected by reset...
  • Page 56 00 = 8-bit truncation mode 01 = Right justified mode 10 = Left justified mode 11 = Left justified sign data mode MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 , correct operation can be guaranteed. See ADIC Characteristics. ADIV[2:0]...

  • Page 57: Chapter 4 Clock Generator Module (Cgm)

    3. Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from CGMOUT. Figure 4-1 shows the structure of the CGM. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...
  • Page 58 $005C (PCTL) See page 66. PLL Bandwidth Control Register $005D (PBWC) See page 67. PLL Programming Register $005E (PPG) See page 68. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 CLOCK SELECT CIRCUIT CGMRCLK CGMXFC VRS[7:4] VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR...

  • Page 59: Crystal Oscillator Circuit

    4.3.2.2 Acquisition and Tracking the reference frequency determines the speed of the corrections and the stability of the PLL. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor , (4.9152 MHz) times a linear factor, L or (L) f...

  • Page 60: Acquisition And Tracking Modes

    • CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling the LOCK bit. For more information, see MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 4.5.2 PLL Bandwidth Control 4.3.3 Base Clock Selector Circuit. The PLL is automatically in 4.3.3 Base Clock Selector...

  • Page 61: Programming The Pll

    Example: N = 4 MHz 4. Calculate the VCO frequency, f Example: f MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor , after entering tracking mode before selecting the PLL as the Table 4-1 lists the variables used and their meaning.

  • Page 62: Special Programming Exceptions

    CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 , and compare f...

  • Page 63: Cgm External Connections

    ) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high-frequency crystals. Refer to the crystal manufacturer’s data for more information. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor CGMXCLK...

  • Page 64: I/O Signals

    4.4.5 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE NOTE should be placed as close to the CGMXFC connection.

  • Page 65: Crystal Output Frequency Signal (Cgmxclk)

    4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 4-3 shows only the logical relation of CGMXCLK to OSC1 4.5.1 PLL Control Register...

  • Page 66: Pll Control Register

    0 = CGMXCLK divided by two drives CGMOUT PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 PLLF PLLON Figure 4-5.

  • Page 67: Pll Bandwidth Control Register

    Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Circuit. LOCK CGM Registers...

  • Page 68: Pll Programming Register

    Table 4-2. VCO Frequency Multiplier (N) Selection MUL7:MUL6:MUL5:MUL4 0000 0001 0010 0011 1101 1110 1111 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 MUL6 MUL5 MUL4 VRS7 4.3.2.4 Programming the PLL. A value of $0 in the multiplier select bits VCO Frequency Multiplier (N) Bit 0...

  • Page 69: Interrupts

    PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE .

  • Page 70: Acquisition/Lock Time Specifications

    This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 – f 4.3.2.3 Manual and Automatic PLL Bandwidth...

  • Page 71: Choosing A Filter Capacitor

    Correct selection of filter capacitor, C • Room temperature operation • Negligible external leakage on C • Negligible noise MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 4.8.3 Choosing a Filter Time, the external filter capacitor, C ⎛ ⎞ ⎜...
  • Page 72 In manual mode, it is usually necessary to wait considerably longer than t clock (see 4.3.3 Base Clock Selector Influences on Reaction Time may slow the lock time considerably. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 is the K factor when the PLL is configured in tracking mode. Modes. ⎛ ⎞...

  • Page 73: Chapter 5 Configuration Register (Config)

    If the LVI module and the LVI reset signal are enabled, a reset occurs when falls to a voltage, V nine consecutive central processor unit (CPU) cycles. Once an LVI reset occurs, the MCU remains in reset until V MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE 5-1.

  • Page 74: Configuration Register

    1 = STOP mode enabled 0 = STOP mode disabled COPD — COP Disable Bit COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 TOPNEG INDEP LVIRST (PWMMC). (PWMMC).

  • Page 75: Chapter 6 Computer Operating Properly (Cop)

    RESET VECTOR FETCH COPCTL WRITE COPD (FROM CONFIG) RESET COPCTL WRITE Note 1. See 14.3.2 Active Resets from Internal MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 13-BIT SIM COUNTER COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Sources.

  • Page 76: I/O Signals

    An internal reset clears the SIM counter and the COP counter. 6.3.5 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 7 Read: Write: Reset: Figure 6-2.

  • Page 77: Copd (Cop Disable)

    Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...
  • Page 78 Computer Operating Properly (COP) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 79: Chapter 7 Central Processor Unit (Cpu)

    Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 80: Accumulator

    The index register can serve also as a temporary data storage location. Read: Write: Reset: X = Indeterminate MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 ACCUMULATOR (A) INDEX REGISTER (H:X) STACK POINTER (SP) PROGRAM COUNTER (PC) V 1 1 H I N Z C...

  • Page 81: Stack Pointer

    The vector address is the address of the first instruction to be executed after exiting the reset state. Read: Write: Reset: MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 7-4. Stack Pointer (SP) NOTE Loaded with vector from $FFFE and $FFFF Figure 7-5.

  • Page 82: Condition Code Register

    The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE Bit 0 Freescale Semiconductor...

  • Page 83: Arithmetic/Logic Unit (Alu)

    CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Arithmetic/Logic Unit (ALU)

  • Page 84: Instruction Set Summary

    Branch if Half Carry Bit Clear BHCS rel Branch if Half Carry Bit Set BHI rel Branch if Higher MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Description V H I N Z C A ← (A) + (M) + (C) A ← (A) + (M) SP ←...
  • Page 85 CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel Clear Carry Bit Clear Interrupt Mask MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Description V H I N Z C PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL PC ←...
  • Page 86 INC opr INCA INCX Increment INC opr,X INC ,X INC opr,SP MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Description V H I N Z C M ← $00 A ← $00 X ← $00 H ← $00 0 – – 0 1 –...
  • Page 87 ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Effect on CCR Description V H I N Z C PC ← Jump Address –...
  • Page 88 SUB opr,X Subtract SUB opr,X SUB ,X SUB opr,SP SUB opr,SP MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Effect on CCR Description V H I N Z C SP ← (SP + 1); Pull (A) – – – – – – INH SP ←...

  • Page 89: Opcode Map

    Indexed, 16-bit offset addressing mode Memory location Negative bit 7.8 Opcode Map Table 7-2. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Description V H I N Z C PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ←...
  • Page 90 Bit Manipulation Branch Read-Modify-Write BRSET0 BSET0 NEGA NEGX BRCLR0 BCLR0 CBEQ CBEQA CBEQX BRSET1 BSET1 BRCLR1 BCLR1 COMA COMX BRSET2 BSET2 LSRA LSRX BRCLR2 BCLR2 STHX LDHX LDHX BRSET3 BSET3 RORA RORX BRCLR3 BCLR3 ASRA ASRX BRSET4 BSET4 BHCC LSLA LSLX BRCLR4 BCLR4...

  • Page 91: Chapter 8 External Interrupt (Irq)

    IRQ module. ACK1 LATCH MODE1 Addr. Register Name IRQ Status/Control Register $003F (ISCR) See page 94. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor SYNCHRO- NIZER IMASK1 HIGH VOLTAGE DETECT Figure 8-1. IRQ Module Block Diagram Bit 7...

  • Page 92: Irq Pin

    $FFFA and $FFFB. • Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, the IRQ1 latch remains set. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE Figure 8-3.)
  • Page 93 FROM RESET I BIT SET? INTERRUPT? FETCH NEXT INSTRUCTION INSTRUCTION? INSTRUCTION? MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR UNSTACK CPU REGISTERS EXECUTE INSTRUCTION Figure 8-3. IRQ Interrupt Flowchart SET I BIT...

  • Page 94: Irq Status And Control Register

    Figure 8-4. IRQ Status and Control Register (ISCR) ACK1 — IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK1 always reads as logic 0. Reset clears ACK1. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE IRQF Bit 0...
  • Page 95 This read-only bit acts as a status flag, indicating an IRQ event occurred. 1 = External IRQ event occurred. 0 = External IRQ event did not occur. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor IRQ Status and Control Register...
  • Page 96 External Interrupt (IRQ) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 97: Chapter 9 Low-Voltage Inhibit (Lvi)

    CPU CLOCK > LVItrip = 0 LOW V DETECTOR < LVItrip = 1 TRPSEL FROM LVISCR MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor voltage falls to the LVI trip voltage. Chapter 5 Configuration Register LVIPWR FROM CONFIG DIGITAL FILTER...

  • Page 98: Polled Lvi Operation

    The trip point (VLVR1 or VLVR2) may be lower than this. See Electrical Characteristics. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 for only one CPU cycle to bring the MCU out of reset. See Reset. The output of the comparator controls the state of the LVIOUT...

  • Page 99: Lvi Status And Control Register

    The WAIT instruction puts the MCU in low power-consumption standby mode. With the LVIPWR bit in the configuration register programmed to 1, the LVI module is active after a WAIT instruction. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor voltages below the V...

  • Page 100: Stop Mode

    9.7 Stop Mode If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 101: Chapter 10 Input/Output (I/O) Ports (Ports)

    (PTC) See page 106. Port D Data Register $0003 (PTD) See page 107. Data Direction Register A $0004 (DDRA) See page 103. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE Bit 7 Read: PTA7 PTA6 PTA5 Write: Reset:...
  • Page 102 Data Direction Register E $000C (DDRE) See page 109. Data Direction Register F $000D (DDRF) See page 110. Figure 10-1. I/O Port Register Summary (Continued) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 7 Read: DDRB7 DDRB6 DDRB5 Write: Reset: Read:...

  • Page 103: Port A

    Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 10-4 shows the port A I/O logic. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PTA6 PTA5...

  • Page 104: Port B

    These read/write bits are software-programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 DDRAx...

  • Page 105: Data Direction Register B

    DDRB Bit PTB Bit 1. X = don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor DDRB5 DDRB4 DDRB3 NOTE...

  • Page 106: Port C

    0 = Corresponding port C pin configured as input Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 PTC6 PTC5...

  • Page 107: Port D

    = Reserved Figure 10-11. Port D Data Register (PTD) PTD[6:0] — Port D Data Bits These read/write bits are software programmable. Reset has no effect on port D data. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor DDRCx RESET PTCx Figure 10-10.

  • Page 108: Port E

    E pins that are being used by the TIMA or TIMB. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Figure 10-12. Port D Input Circuit Table 10-4 Table 10-4.

  • Page 109: Data Direction Register E

    DDRE Bit PTE Bit 1. X = don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor DDRE5 DDRE4 DDRE3 NOTE...

  • Page 110: Port F

    0 = Corresponding port F pin configured as input Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from 0 to 1. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 PTF5 PTF4...
  • Page 111 DDRF Bit PTF Bit 1. X = don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor DDRFx RESET PTFx Figure 10-18. Port F I/O Circuit Table 10-6 summarizes the operation of the port F pins.
  • Page 112 Input/Output (I/O) Ports (PORTS) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 113: Chapter 11 Power-On Reset (Por)

    The POR is not a brown-out detector, low-voltage detector, or glitch detector. V at the POR must go completely to 0 to reset the microcontroller unit (MCU). To detect power-loss conditions, use a low-voltage inhibit module (LVI) or other suitable circuit. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...
  • Page 114 Power-On Reset (POR) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 115: Chapter 12 Pulse-Width Modulator For Motor Control (Pwmmc)

    Dead-time insertion – Separate top/bottom pulse width correction via current sensing or programmable software bits MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ) and a programmable prescaler. The highest resolution for = 8 MHz). The highest resolution for center-aligned operation is Figure 12-3.
  • Page 116 M68HC08 CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE CGMXFC SYSTEM INTEGRATION MODULE MODULE...
  • Page 117 Fault Acknowledge Register $0024 (FTACK) See page 153. Figure 12-3. Register Summary (Sheet 1 of 3) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PWM CHANNELS 1 AND 2 PWM CHANNELS 3 AND 4 PWM CHANNELS 5 AND 6...
  • Page 118 PWM 3 Value Register High $002E (PVAL3H) See page 145. PWM 3 Value Register Low $002F (PVAL3L) See page 145. Figure 12-3. Register Summary (Sheet 2 of 3) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 7 Read: OUTCTL OUT6 Write: Reset: Read: Write:...
  • Page 119 See page 150. PWM Disable Mapping $0037 Write-Once Register (DISMAP) See page 150. Figure 12-3. Register Summary (Sheet 3 of 3) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Bit 7 Read: Bit 15 Bit 14 Bit 13 Write:...

  • Page 120: Timebase

    PWM = 1 PWM = 2 PWM = 3 PWM = 4 Figure 12-4. Center-Aligned PWM (Positive Polarity) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 PERIOD = 8 X (PWM CLOCK PERIOD) = 8 MHz) as shown in Freescale Semiconductor...
  • Page 121 Center-aligned operation versus edge-aligned operation is determined by the option EDGE. See Functional Description. UP-ONLY COUNTER Figure 12-5. Edge-Aligned PWM (Positive Polarity) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor (timer modulus) x (PWM clock period) MODULUS = 4 PERIOD = 4 X (PWM...

  • Page 122: Prescaler

    PWMF is set. Software can use this interrupt to calculate new PWM parameters in real time for the PWM module. Reload Frequency Bits LDFQ1 and LDFQ0 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Table 12-1. PWM Prescaler PWM Clock Frequency Table 12-2. PWM Reload Frequency...
  • Page 123 LDOK bit is set. Even if it is not set, an interrupt will occur if the PWMINT bit is set. To prevent this, the software should clear the PWMINT bit before enabling the PWM module. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE...
  • Page 124 LDOK = 1 MODULUS = 3 PWM VALUE = 1 PWMF SET Figure 12-10. Edge-Aligned PWM Value Loading MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 LDFQ1:LDFQ0 = 00 (RELOAD EVERY CYCLE) LDOK = 1 LDOK = 0 MODULUS = 3...

  • Page 125: Pwm Data Overflow And Underflow Conditions

    PWM pins. Table 12-3. PWM Data Overflow and Underflow Conditions PWMVALxH:PWMVALxL $0000–$0FFF $1000–$7FFF $8000–$FFFF MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor LDFQ1:LDFQ0 = 00 (RELOAD EVERY CYCLE) LDOK = 1 LDOK = 1 MODULUS = 4...

  • Page 126: Output Control

    PWM value register. This type of operation is meant for use in motor drive circuits such as the one in PWM VALUE REGISTER PWM VALUE REGISTER PWM VALUE REGISTER INPUTS MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Figure 12-13. PWMS 1 AND 2 PWMS 3 AND 4 PWMS 5 AND 6 Figure 12-12.

  • Page 127: Dead-Time Insertion

    Figure 12-17 shows the effects of dead-time insertion on pulse widths smaller than the dead-time. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 12-13, if PWM1 and PWM2 were on at the same time, large currents 12-14. Current sensing determines which PWM value of a PWM generator 12.5.3 Top/Bottom Correction with Motor Phase...
  • Page 128 Pulse-Width Modulator for Motor Control (PWMMC) OUTPUT CONTROL (OUTCTL) PWMPAIR12 (TOP) PWMPAIR34 (TOP) PWMPAIR56 (TOP) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 OUT2 OUT4 OUT6 PWM (TOP) DEAD-TIME POSTDT (TOP) PREDT (TOP) OUTX SELECT PWM (TOP) DEAD-TIME PREDT (TOP) POSTDT (TOP)
  • Page 129 PWM1 W/ DEAD-TIME = 2 PWM2 W/ DEAD-TIME = 2 Figure 12-16. Dead-Time at Duty Cycle Boundaries MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PWM VALUE = 2 PWM VALUE = 1 PWM VALUE = 3 Output Control...

  • Page 130: Top/Bottom Correction With Motor Phase Current Polarity Sensing

    This distortion is aggravated by dissimilar turn-on and turn-off delays of each of the transistors. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 PWM VALUE = 3 PWM VALUE = 2...
  • Page 131 PWMs are PWMs 2, 4, and 6. Current Sense Pin or Bit IS1 or IPOL1 IS1 or IPOL1 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 12-13, for a given top/bottom transistor pair, only one Table NOTE Figure 12-19 for current convention.
  • Page 132 When the PWM is first enabled by setting PWMEN, PWM value registers 1, 3, and 5 will be used if the ISENSx bits are configured for current sensing correction. This is because no current will have previously been sensed. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Table 12-5.

  • Page 133: Output Polarity

    Both bits are found in the CONFIG register, which is a write-once register. This reduces the chances of the software inadvertently changing the polarity of the PWM signals and possibly damaging the motor drive hardware. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PWM VALUE REG. 2 = 2 IS1 NEGATIVE...
  • Page 134 MODULUS = 4 PWM <= 0 PWM = 1 PWM = 2 PWM = 3 PWM >= 4 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 EDGE-ALIGNED POSITIVE POLARITY UP-ONLY COUNTER MODULUS = 4 PWM <= 0 PWM = 1 PWM = 2 PWM = 3 PWM >= 4...

  • Page 135: Pwm Output Port Control

    PWM cycle. To avoid an unexpected dead-time occurrence, it is recommended that the OUTx bits be cleared prior to entering and prior to exiting individual PWM output control mode. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 12-22.
  • Page 136 OUT2 PWM1 PWM2 PWM1/PWM2 DEAD-TIME Figure 12-24. Dead-Time Insertion During OUTCTL = 1 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 DEAD-TIME INSERTED DUE TO SETTING OF OUT1 BIT DEAD-TIME INSERTED BECAUSE DEAD-TIME INSERTED WHEN OUTCTL WAS SET, THE BECAUSE OUT1 TOGGLES,...

  • Page 137: Fault Protection

    Automatic mode is selected by setting the FMODEx bit in the fault control register. Manual mode is selected when FMODEx is clear. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor shows the structure of the PWM disabling scheme. While the PWM pins...
  • Page 138 The example is of fault pin 1. Fault pin 3 is logically similar and affects BANK Y disable. Note: In manual mode (FMODE = 0), faults 1 and 3 may be cleared regardless of the logic level at the input of the fault pin. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 DISX...

  • Page 139: Fault Pin Filter

    The FFLAGx bit is cleared by writing a 1 to the corresponding FTACKx bit. • The FINTx bit is cleared. This will not clear the FFLAGx bit. • A reset automatically clears all four interrupt latches. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor BIT 7 BIT 6 BIT 5...

  • Page 140: Manual Mode

    FFLAGx event bit is cleared by writing to the FTACKx bit and the filtered fault condition is cleared (logic low). FILTERED FAULT PIN 1 OR 3 PWM(S) ENABLED Figure 12-29. PWM Disabling in Manual Mode (Example 1) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 PWM(S) DISABLED (INACTIVE) NOTE Figure 12-30.

  • Page 141: Software Output Disable

    Due to the absence of periodic PWM cycles, fault conditions are cleared upon each CPU cycle and the PWM outputs are re-enabled, provided all fault clearing conditions are satisfied. DISABLE BIT PWM(S) ENABLED PWM(S) DISABLED PWM(S) ENABLED Figure 12-31. PWM Software Disable MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 142: Initialization And The Pwmen Bit

    • Dead-time insertion when PWM pins change via the PWMOUT register The PWMF flag and pending CPU interrupts are NOT cleared when PWMEN = 0. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE 12.9.2 PWM Counter Modulo 12-32. DRIVE ACCORDING TO PWM VALUE, POLARITY, AND DEAD-TIME Figure 12-32.

  • Page 143: Pwm Operation In Wait Mode

    $0027 Bit 7 Read: Bit 7 Write: Reset: = Unimplemented Figure 12-34. PWM Counter Register Low (PCNTL) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 12-34. Bit 11 Bit 6 Bit 5 Bit 4 Bit 3 PWM Operation in Wait Mode...

  • Page 144: Pwm Counter Modulo Registers

    $FFF. This operation will not be tested or guaranteed (the user should consider it illegal). However, the dead-time constraints and fault conditions will still be guaranteed. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Figure 12-36.

  • Page 145: Pwmx Value Registers

    LDOK bit has been set and the next PWM load cycle begins. When reading these registers, the value read is the buffer (not necessarily the value the PWM generator is currently using). MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Bit 14...

  • Page 146: Pwm Control Register 1

    When PWMF is cleared, pending PWM CPU interrupts are cleared (not including fault interrupts). ISENS1 and ISENS0 — Current Sense Correction Bits These read/write bits select the top/bottom correction scheme as shown in MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 DISY PWMINT PWMF...
  • Page 147 For more information, see 12.7 Initialization and the PWMEN 1 = PWM generator and PWM pins enabled 0 = PWM generator and PWM pins disabled MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Table 12-7. Correction Methods Correction Method Bits IPOL1, IPOL2, and IPOL3 are used for correction.

  • Page 148: Pwm Control Register 2

    This buffered read/write bit selects which PWM value register is used if top/bottom correction is to be achieved without current sensing. 1 = Use PWM value register 2. 0 = Use PWM value register 1. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE LDFQ0 IPOL1...
  • Page 149 These buffered read/write bits allow the PWM clock frequency to be modified as shown in When reading these bits, the value read is the buffer value (not necessarily the value the PWM generator is currently using). Prescaler Bits PRSC1 and PRSC0 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE NOTE NOTE NOTE Table 12-9.

  • Page 150: Dead-Time Write-Once Register

    1 = Fault pin 4 will cause CPU interrupts. 0 = Fault pin 4 will not cause CPU interrupts. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 6 Bit 5...
  • Page 151 This read/write bit allows the user to select between automatic and manual mode faults. For further descriptions of each mode, see 1 = Automatic mode 0 = Manual mode MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 12.6 Fault Protection.

  • Page 152: Fault Status Register

    This read-only bit allows the user to read the current state of fault pin 1. 1 = Fault pin 1 is at logic 1. 0 = Fault pin 1 is at logic 0. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 FPIN3 FFLAG3...

  • Page 153: Fault Acknowledge Register

    Current sensing pin IS2 is monitored immediately before dead-time ends due to the assertion of PWM4. DT3 — Dead-Time 3 Bit Current sensing pin IS2 is monitored immediately before dead-time ends due to the assertion of PWM3. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor FTACK3 Control Logic Block Bit 0...

  • Page 154: Pwm Output Control Register

    1 — PWM5 is active. OUT5 0 — PWM5 is inactive. 1 — PWM 6 is complement of PWM 5. OUT6 0 — PWM6 is inactive. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 OUT6 OUT5 OUT4 Table Table 12-10. OUTx Bits...

  • Page 155: Pwm Glossary

    • Edge-aligned mode: The time it takes the PWM counter to count up (modulus/f 12-47. PWM CLOCK CYCLE Figure 12-47. PWM Clock Cycle and PWM Cycle Definitions MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 12-47. Center-Aligned Mode...
  • Page 156 LDFQ1:LDFQ0 = 01 — Reload Every Two Cycles RELOAD NEW MODULUS, PRESCALER, & PWM VALUES IF LDOK = 1 Figure 12-48. PWM Load Cycle/Frequency Definition MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 PWM LOAD CYCLE (1/PWM LOAD FREQUENCY) RELOAD NEW MODULUS, PRESCALER, & PWM VALUES IF...

  • Page 157: Chapter 13 Serial Communications Interface Module (Sci)

    Receiver full – Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...
  • Page 158 M68HC08 CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE CGMXFC SYSTEM INTEGRATION MODULE MODULE...

  • Page 159: Functional Description

    SCI DATA REGISTER RECEIVE PTF4/RxD SHIFT REGISTER SCTIE TCIE SCRIE ILIE WAKEUP CONTROL ÷ 4 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor INTERNAL BUS SCTE SCRF IDLE LOOPS RECEIVE FLAG CONTROL CONTROL ENSCI PRE- BAUD RATE...

  • Page 160: Data Format

    13.3.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in START BIT 0 BIT 1 START BIT 0 BIT 1 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 7 Read: LOOPS ENSCI TXINV Write: Reset: Read:...

  • Page 161: Transmitter

    PRE- BAUD ÷ 4 SCALER DIVIDER SCP1 SCP0 SCR2 SCR1 SCR0 TRANSMITTER CPU INTERRUPT REQUEST MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor INTERNAL BUS ÷ 16 SCI DATA REGISTER 11-BIT TRANSMIT SHIFT REGISTER TXINV PARITY GENERATION SCTE SCTE...

  • Page 162: Character Length

    Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception-in-progress flag (RPF) bits MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 163: Idle Characters

    TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. 13.3.3 Receiver Figure 13-6 shows the structure of the SCI receiver. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE Functional Description...

  • Page 164: Character Length

    (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 INTERNAL BUS...

  • Page 165: Character Reception

    To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 13-1 summarizes the results of the start bit verification samples. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor START BIT...
  • Page 166 To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. summarizes the results of the stop bit samples. RT8, RT9, and RT10 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Table 13-1. Start Bit Verification Start Bit...

  • Page 167: Framing Errors

    SCDR. The previous character remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE...

  • Page 168: Wait Mode

    The PTF5/TxD pin is the serial data output from the SCI transmitter. The SCI shares the PTF5/TxD pin with port F. When the SCI is enabled, the PTF5/TxD pin is an output regardless of the state of the DDRF5 bit in data direction register F (DDRF). MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 169: Ptf4/Rxd (Receive Data)

    SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ENSCI TXINV WAKE...
  • Page 170 1 = Odd parity 0 = Even parity Changing the PTY bit in the middle of a transmission or reception can generate a parity error. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE Table 13-4. When enabled, the parity function Figure 13-4.

  • Page 171: Sci Control Register 2

    This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Table 13-4. Character Format Selection Character Format...
  • Page 172 0 = No break characters being transmitted Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK too early causes the SCI to send a break character instead of a preamble. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE NOTE NOTE...

  • Page 173: Sci Control Register 3

    This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. 13.7.4 SCI Status Register 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ORIE U = Unaffected 1.

  • Page 174: Sci Status Register 1

    SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 SCRF IDLE Bit 0...
  • Page 175 OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. BYTE 1 READ SCS1 READ SCDR BYTE 1 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NORMAL FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1...

  • Page 176: Sci Status Register 2

    SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the PTF4/RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 0 Freescale Semiconductor...

  • Page 177: Sci Data Register

    Figure 13-15. SCI Baud Rate Register (SCBR) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in and SCP0. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Unaffected by reset SCP1 SCP0 Table 13-5.
  • Page 178 SCI baud rates that can be generated with a 4.9152-MHz crystal with the CGM set for an f of 7.3728 MHz and the CGM set for an f MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Table 13-6. SCI Baud Rate Selection Baud Rate Divisor (BD)
  • Page 179 Table 13-7. SCI Baud Rate Selection Examples Prescaler SCP1:SCP0 Divisor (PD) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Baud Rate SCR2:SCR1:SCR0 Divisor (BD) I/O Registers Baud Rate Baud Rate = 7.3728 MHz) = 4.9152 MHz) 115,200 76,800 57,600...
  • Page 180 Serial Communications Interface Module (SCI) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 181: Chapter 14 System Integration Module (Sim)

    PLL-based or OSC1-based clock output from CGM module (bus clock = CGMOUT divided by two) Internal address bus Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal Read/write signal MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 14-1. Table 14-1. Signal Name Conventions Description...

  • Page 182: Sim Bus Clock Control And Generation

    CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The internal bus (IBUS) clocks start upon completion of the timeout. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 WAIT CONTROL COUNTER ÷...

  • Page 183: Clocks In Wait Mode

    (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See timing. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor CGMXCLK...

  • Page 184: Active Resets From Internal Sources

    The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Table 14-2. PIN Bit Set Timing Number of Cycles Required to Set PIN...

  • Page 185: Power-On Reset (Por)

    The COP module is disabled if the RST pin or the IRQ pin is held at V The COP module can be disabled only through combinational logic conditioned with the high voltage MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 186: Illegal Opcode Reset

    External reset has no effect on the SIM counter. The SIM counter is free-running after all reset states. For counter control and internal reset recovery sequences, see 14.3.2 Active Resets from Internal Sources. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 187: Exception Control

    CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). See MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 14-9 shows interrupt recovery timing.
  • Page 188 System Integration Module (SIM) AS MANY INTERRUPTS AS EXIST ON CHIP MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 FROM RESET BREAK OR SWI I BIT SET? INTERRUPT? I BIT SET? INTERRUPT? STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR FETCH NEXT...

  • Page 189: Hardware Interrupts

    If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor SP – 3 SP –...

  • Page 190: Software Interrupt (Swi) Instruction

    Figure 14-12 Figure 14-13 EXITSTOPWAIT Note: EXITSTOPWAIT = RST pin OR CPU interrupt Figure 14-12. Wait Recovery from Interrupt MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 14-11. Wait Mode Entry Timing show the timing for wait recovery.

  • Page 191: Stop Mode

    Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Wait mode was exited by break interrupt. 0 = Wait mode was not exited by break interrupt. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor CYCLES CYCLES Note 1.

  • Page 192: Sim Reset Status Register

    0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 ILOP ILAD Bit 0...

  • Page 193: Sim Break Flag Control Register

    To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor SIM Registers...
  • Page 194 System Integration Module (SIM) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 195: Chapter 15 Serial Peripheral Interface Module (Spi)

    The generic pin names appear in the text that follows. Table 15-1 Generic Pin Names: Full Pin Names: MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor shows the full names of the SPI I/O pins. Table 15-1. Pin Name Conventions MISO...
  • Page 196 M68HC08 CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE CGMXFC SYSTEM INTEGRATION MODULE MODULE...

  • Page 197: Functional Description

    DIVIDER ÷ 32 ÷ 128 CLOCK SPMSTR SELECT SPR1 TRANSMITTER CPU INTERRUPT REQUEST RECEIVER/ERROR CPU INTERRUPT REQUEST MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 15-3 INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER RECEIVE DATA REGISTER SPR0 SPMSTR...

  • Page 198: Master Mode

    MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 7...

  • Page 199: Slave Mode

    SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 15.6.2 Mode Fault...

  • Page 200: Transmission Format When Cpha = 0

    CAPTURE STROBE Figure 15-5. Transmission Format (CPHA = 0) MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE Figure 15-6. BIT 6 BIT 5 BIT 4 BIT 3...

  • Page 201: Transmission Format When Cpha = 1

    SPSCK signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...
  • Page 202 WRITE TO SPDR CLOCK EARLIEST Figure 15-8. Transmission Start Delay (Master) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Figure 15-8 The internal SPI clock in the master is a free-running INITIATION DELAY INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN SPSCK = INTERNAL CLOCK ÷...

  • Page 203: Error Conditions

    CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT. Figure 15-9. Missed Read of Overflow Condition MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor BYTE 2 BYTE 3 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR.

  • Page 204: Mode Fault Error

    The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. MODF and OVRF can generate a receiver/error CPU interrupt request. See MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Figure 15-10 illustrates this process. Generally, to avoid this second...
  • Page 205 To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This entire clearing procedure must occur with no MODF condition existing or else the flag is not cleared. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE 15.5 Transmission...

  • Page 206: Interrupts

    If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE can generate either an SPTE or CPU interrupt request. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Table 15-2. SPI Interrupts Request...

  • Page 207: Resetting The Spi

    This implies that a back-to-back write to the transmit data register is not possible. The SPTE indicates when the next write can occur. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Resetting the SPI...

  • Page 208: Low-Power Mode

    • MOSI — Data transmitted • SPSCK — Serial clock • SS — Slave select MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 MSBBIT LSBMSBBIT BYTE 1 BYTE 2 7 CPU READS SPDR, CLEARING SPRF BIT. CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE 3 AND CLEARING SPTE BIT.

  • Page 209: Miso (Master In/Slave Out)

    SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor C) capability (requiring software support) as a master in a C peripherals, MOSI becomes an open-drain output C communication, the MOSI and MISO pins...

  • Page 210: Vss (Clock Ground)

    Selects serial clock polarity and phase • Configures the SPSCK, MOSI, and MISO pins as open-drain outputs • Enables the SPI module MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 15.12.2 SPI Status and Control NOTE 15.6.2 Mode Fault Table 15-3.
  • Page 211 This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor SPMSTR CPOL...

  • Page 212: Spi Status And Control Register

    This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests. 0 = MODF and OVRF cannot generate CPU interrupt requests. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 OVRF MODF SPTE...
  • Page 213 SPR1 and SPR0 — SPI Baud Rate Select Bits In master mode, these read/write bits select one of four baud rates as shown in SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE Select).

  • Page 214: Spi Data Register

    R7:R0/T7:T0 — Receive/Transmit Data Bits Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Baud Rate Divisor (BD) CGMOUT Baud rate ------------------------- - ×...

  • Page 215: Chapter 16 Timer Interface A (Tima)

    7-frequency internal bus clock prescaler selection – External TIMA clock input (4-MHz maximum frequency) • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIMA counter stop and reset bits MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...
  • Page 216 M68HC08 CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE CGMXFC SYSTEM INTEGRATION MODULE MODULE...
  • Page 217 CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH CHANNEL 2 16-BIT COMPARATOR TCH2H:TCH2L 16-BIT LATCH CHANNEL 3 16-BIT COMPARATOR TCH3H:TCH3L 16-BIT LATCH MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PRESCALER SELECT ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A CH1F MS1A...
  • Page 218 See page 232. TIMA Channel 1 Register Low $0018 (TACH1L) See page 232. TIMA Channel 2 Status/Control $0019 Register (TASC2) See page 229. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 7 Read: TOIE TSTOP Write: Reset: Read: Bit 15...

  • Page 219: Functional Description

    The level transition which triggers the counter transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0–TASC3 control registers with MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 220: Output Compare

    Also, using a TIMA overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIMA may pass the new value before it is written. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 221: Buffered Output Compare

    TIMA channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMA MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 222: Unbuffered Pwm Signal Generation

    PWM period. In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0 percent MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 16.7.1 TIMA Status and Control OVERFLOW...

  • Page 223: Buffered Pwm Signal Generation

    2. In the TIMA counter modulo registers (TAMODH–TAMODL), write the value for the required PWM period. 3. In the TIMA channel x registers (TACHxH–TACHxL), write the value for the required pulse width. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE...

  • Page 224: Interrupts

    Channel x TIMA CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. 16.5 Wait Mode The WAIT instruction puts the MCU in low power-consumption standby mode. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE 16.7.4 TIMA Channel Status and Control Table 16-2.)

  • Page 225: I/O Signals

    The TIMA status and control register: • Enables TIMA overflow interrupts • Flags TIMA overflows • Stops the TIMA counter • Resets the TIMA counter • Prescales the TIMA counter clock MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Register. I/O Signals...
  • Page 226 0. Reset clears the TRST bit. 1 = Prescaler and TIMA counter cleared 0 = No effect Setting the TSTOP and TRST bits simultaneously stops the TIMA counter at a value of $0000. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 TOIE TSTOP TRST NOTE...

  • Page 227: Tima Counter Registers

    Bit 7 Write: Reset: = Reserved Figure 16-6. TIMA Counter Registers (TACNTH and TACNTL) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor pin or one of the seven prescaler outputs as the PTE3/TCLKA Table 16-1 shows. Reset clears the PS[2:0] bits.

  • Page 228: Tima Counter Modulo Registers

    Selects output toggling on TIMA overflow • Selects 0 percent and 100 percent PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 TAMODH — $0011 Bit 14 Bit 13 Bit 12 Bit 11 TAMODL —...
  • Page 229 This read/write bit enables TIMA CPU interrupts on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor TASC0 — $0013 CH0IE...
  • Page 230 ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Before enabling a TIMA channel register for input capture operation, make sure that the PTEx/TACHx pin is stable for at least two bus clocks. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Table 16-2.
  • Page 231 PERIOD PTEx/TCHx OUTPUT COMPARE CHxMAX TOVx MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Mode Pin under port control; initialize timer output level high Output preset Pin under port control; initialize timer output level low Capture on rising edge only...

  • Page 232: Tima Channel Registers

    Register Name and Address: Bit 7 Read: Bit 15 Write: Reset: Figure 16-10. TIMA Channel Registers MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 TACH0H — $0014 Bit 14 Bit 13 Bit 12 Bit 11 Indeterminate after reset TACH0L — $0015...
  • Page 233 Reset: Register Name and Address: Bit 7 Read: Bit 7 Write: Reset: Figure 16-10. TIMA Channel Registers MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor TACH2L — $001B Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset TACH3H —...
  • Page 234 Timer Interface A (TIMA) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 235: Chapter 17 Timer Interface B (Timb)

    The two TIMB channels are programmable independently as input capture or output compare channels. The TIMB module is not available in the 56-pin SDIP. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE...
  • Page 236 M68HC08 CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE CGMXFC SYSTEM INTEGRATION MODULE MODULE...
  • Page 237 TIMB Counter Modulo Register $0054 High (TBMODH) See page 246. TIMB Counter Modulo Register $0055 Low (TBMODL) See page 246. Figure 17-3. TIMB I/O Register Summary MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PRESCALER SELECT ELS0B ELS0A CH0F MS0A MS0B ELS1B...

  • Page 238: Timb Counter Prescaler

    The free-running counter contents are transferred to the TIMB channel status and control register (TBCHxH–TBCHxL, see 17.7.5 TIMB Channel MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Bit 7 Read: CH0F...

  • Page 239: Output Compare

    Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Functional Description 17.7.5 TIMB Channel...

  • Page 240: Buffered Output Compare

    PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIMB counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000 (see MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE OVERFLOW...

  • Page 241: Unbuffered Pwm Signal Generation

    1 pin, PTE2/TCH1B, is available as a general-purpose I/O pin. In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE...

  • Page 242: Pwm Initialization

    The result is a 0 percent duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100 percent duty cycle output. (See MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE 17.7.4 TIMB Channel Status and Control Table 17-2.)

  • Page 243: Interrupts

    Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTE1/TCH0B and PTE2/TCH1B can be configured as buffered output compare or buffered PWM pins. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Register.

  • Page 244: I/O Registers

    This read/write bit enables TIMB overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIMB overflow interrupts enabled 0 = TIMB overflow interrupts disabled MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 TOIE TSTOP TRST...
  • Page 245 PS[2:0] — Prescaler Select Bits These read/write bits select either the PTE0/TCLKB pin or one of the seven prescaler outputs as the input to the TIMB counter as PS[2:0] MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE NOTE Table 17-1 shows.

  • Page 246: Timb Counter Registers

    Bit 7 Write: Reset: Figure 17-7. TIMB Counter Modulo Registers (TBMODH and TBMODL) Reset the TIMB counter before writing to the TIMB counter modulo registers. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE TBCNTH — $0052 Bit 14 Bit 13...

  • Page 247: Timb Channel Status And Control Registers

    This read/write bit enables TIMB CPU interrupts on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor TBSC0 — $0056 CH0IE...
  • Page 248 TIMB counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIMB counter overflow. 0 = Channel x pin does not toggle on TIMB counter overflow. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Table 17-2. Table 17-2.
  • Page 249 PERIOD PTEx/TCHx OUTPUT COMPARE CHxMAX TOVx MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Mode Pin under port control; initialize timer output level high Output preset Pin under port control; initialize timer output level low Capture on rising edge only...

  • Page 250: Timb Channel Registers

    Register Name and Address: Bit 7 Read: Bit 7 Write: Reset: Figure 17-10. TIMB Channel Registers (TBCH0H/L–TBCH1H/L) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 TBCH0H — $0057 Bit 14 Bit 13 Bit 12 Bit 11 Indeterminate after reset TBCH0L — $0058...

  • Page 251: Chapter 18 Development Support

    18.2.1.1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...
  • Page 252 Break Status and Control $FE0E Register (BRKSCR) Write: See page 254. Reset: Note: Writing a 0 clears BW. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 IAB15–IAB8 BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB7–IAB0 Bit 7...

  • Page 253: Cpu During Break Interrupts

    Break address register high (BRKH) • Break address register low (BRKL) • SIM break status register (SBSR) • SIM break flag control register (SBFCR) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor is present on the RST pin. Break Module (BRK)

  • Page 254: Break Status And Control Register

    Figure 18-4. Break Address Register High (BRKH) Address: $FE0D Bit 7 Read: Bit 7 Write: Reset: Figure 18-5. Break Address Register Low (BRKL) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 BRKA Bit 0 Bit 0 Bit 8 Bit 0 Bit 0 Freescale Semiconductor...

  • Page 255: Break Status Register

    Monitor mode entry can be achieved without the use of V vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Monitor ROM (MON)

  • Page 256: Functional Description

    COP is a mask option enabled or disabled by the COPD bit in the configuration register. 18.3.1.2 Normal Monitor Mode Table 18-2 shows the pin conditions for entering monitor mode. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 NOTE Table 18-1. Mode Differences Functions...
  • Page 257 S2 Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4 S2 Position B — Bus clock = CGMXCLK ÷ 2 S3 Position A — Parallel communication S3 Position B — Serial communication MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 10 µF 10 µF...
  • Page 258 Table 18-2. Monitor Mode Signal Requirements and Options RESET $FFFE PTC2 PLL PTC3 PTC4 (S1) /$FFFF (S2) $FFFF Blank $FFFF Blank Non-$FF Programmed 1. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator. 2. DNA = does not apply, X = don’t care 3.

  • Page 259: Forced Monitor Mode

    Figure 18-10. Sample Monitor Waveforms The data transmit and receive rate can be anywhere from 4800 baud to 28.8 Kbaud. Transmit and receive baud rates must be identical. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Chapter 14 System Integration Module (SIM) the MCU will come out of reset in user mode.

  • Page 260: Echoing

    IREAD, indexed read • IWRITE, indexed write • READSP, read stack pointer • RUN, run user program MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 READ ADDR. HIGH ADDR. HIGH ADDR. LOW Figure 18-11. Read Transaction Figure MISSING STOP BIT 2--STOP-BIT DELAY BEFORE ZERO ECHO Figure 18-12.
  • Page 261 Read next 2 bytes in memory from last address accessed Operand 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode ECHO MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS...
  • Page 262 FROM HOST ECHO Table 18-8. RUN (Run User Program) Command Description Executes PULH and RTI instructions Operand None Data Returned None Opcode MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO Command Sequence READSP...

  • Page 263: Baud Rate

    RAM. The bulk erase operation clears the security code locations so that all eight security bytes become $FF. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor VCO Frequency Multiplier (N)
  • Page 264 2 = Data return delay, 2 bit times 3 = Wait 1 bit time before sending next byte. Figure 18-13. Monitor Mode Entry Timing MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 24 BUS CYCLES 256 BUS CYCLES (MINIMUM) Freescale Semiconductor...

  • Page 265: Chapter 19 Electrical Specifications

    V ≤ (V or V inputs are connected to an appropriate logic voltage level (for example, either V or V MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE Characteristics. and V NOTE and V be constrained to the range ) ≤...

  • Page 266: Functional Operating Range

    1. Power dissipation is a function of temperature. 2. K is a constant unique to the device. K can be determined for a known T can be determined for any value of T MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Symbol Symbol θ...

  • Page 267: Dc Electrical Characteristics

    POR is released, RST must be driven low externally until minimum V is reached. 9. Maximum is highest voltage that POR is possible. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Symbol LVR1...

  • Page 268: Flash Memory Characteristics

    4. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Symbol —...

  • Page 269: Serial Peripheral Interface Characteristics

    2. Numbers refer to dimensions in Figure 19-1 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Serial Peripheral Interface Characteristics Symbol OP(M)
  • Page 270 MISO INPUT MOSI OUTPUT Note: This last clock edge is generated internally, but is not seen at the SCK pin. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 MSB IN BITS 6–1 MASTER MSB OUT BITS 6–1 a) SPI Master Timing (CPHA = 0) MSB IN BITS 6–1...
  • Page 271 INPUT MISO NOTE INPUT MOSI OUTPUT Note: Not defined, but normally LSB of character previously transmitted MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor MSB OUT BITS 6–1 BITS 6–1 a) SPI Slave Timing (CPHA = 0) SLAVE MSB OUT BITS 6–1...

  • Page 272: Timer Interface Module Characteristics

    19.11 CGM Operating Conditions Characteristic Crystal reference frequency Range nominal multiplier VCO center-of-range frequency VCO frequency multiplier VCO center of range multiplier VCO operating frequency MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Symbol TIH, TCH, Symbol — — 2 * C —...

  • Page 273: Cgm Acquisition/Lock Time Specifications

    Automatic mode time to stable Automatic stable to lock time Automatic lock time PLL jitter (deviation of average bus frequency over 2 ms) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor CGM Acquisition/Lock Time Specifications Symbol — 0.0154 FACT —...

  • Page 274: Analog-To-Digital Converter (Adc) Characteristics

    Monotonicity Zero input reading Full-scale reading Input capacitance current REFH REFL Absolute accuracy (8-bit truncation mode) Quantization error (8-bit truncation mode) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Symbol — DDAD — ADIN DDAD — ± 4 — — 500 k —...

  • Page 275: Chapter 20 Ordering Information And Mechanical Specifications

    Chapter 20 Ordering Information and Mechanical Specifications 20.1 Introduction This section provides ordering information for the MC68HC908MR16 and MC68HC908MR32 along with the dimensions for: • 64-lead plastic quad flat pack (QFP) • 56-pin shrink dual in-line package (SDIP) The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Freescale Sales Office.

  • Page 276: 64-Pin Plastic Quad Flat Pack (Qfp)

    Ordering Information and Mechanical Specifications 20.3 64-Pin Plastic Quad Flat Pack (QFP) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 277: 56-Pin Shrink Dual In-Line Package (Sdip)

    56-Pin Shrink Dual In-Line Package (SDIP) 20.4 56-Pin Shrink Dual In-Line Package (SDIP) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...
  • Page 278 Ordering Information and Mechanical Specifications MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...

  • Page 279: Appendix A Mc68Hc908Mr16

    Appendix A MC68HC908MR16 The information contained in this document pertains to the MC68HC908MR16 with the exception of that shown in Figure A-1. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor...
  • Page 280 ↓ $FFD1 $FFD2 ↓ $FFFF Figure A-1. MC68HC908MR16 Memory Map MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 I/O REGISTERS — 96 BYTES RAM — 768 BYTES UNIMPLEMENTED — 31,904 BYTES FLASH — 16,128 BYTES UNIMPLEMENTED — 16,128 BYTES SIM BREAK STATUS REGISTER (SBSR)
  • Page 282 Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.

This manual is also suitable for:

Mc68hc908mr32

Table of Contents