Freescale Semiconductor MCF54455 Reference Manual page 201

Power Management
There are several options for enabling or disabling the PLL or crystal oscillator in stop mode,
compromising between stop mode current and wake-up recovery time. The PLL can be disabled in stop
mode, but requires a wake-up period before it can relock. The oscillator can also be disabled during stop
mode, but requires a wake-up period to restart.
When the PLL is enabled in stop mode (LPCR[STPMD] = 00), the external FB_CLK signal can support
systems using FB_CLK as the clock source. See
for more information about operating the PLL in stop mode.
There is also a fast wake-up option for quickly enabling the system clocks during stop recovery
(LPCR[FWKUP]). This eliminates the wake-up recovery time but at the risk of sending a potentially
unstable clock to the system. This is also explained in
(LPCR)."
9.3.4.4 Chip Configuration Module
The chip configuration module is unaffected by entry into a low-power mode. If a reset exits low-power
mode, chip configuration may execute if configured to do so.
9.3.4.5 Reset Controller
A power-on reset (POR) always causes a chip to reset and exit from any low-power mode.
In wait and doze modes, asserting the external RESET pin for at least four clocks causes an external reset
that resets the chip and exits any low-power modes.
In stop mode, the RESET pin synchronization disables and asserting the external RESET pin
asynchronously generates an internal reset and exit any low-power modes. Registers lose current values
and must be reconfigured from reset state if needed.
If the core watchdog timer is still enabled during wait or doze modes, a watchdog timer timeout may
generate a reset to exit these low-power modes.
When the CPU is inactive, a software reset cannot generate to exit any low-power mode.
9.3.4.6 System Control Module (SCM)
The SCM's core watchdog timer can bring the device out of all low-power modes except stop mode. In
stop mode, all clocks stop, and the core watchdog timer does not operate.
When enabled, the core watchdog can bring the device out of low-power mode in one of two ways.
Depending on the setting of the CWCR[CWRI] field, a core watchdog timeout may reset the device. Other
settings of the CWRI field may enable a core watchdog interrupt and upon a watchdog timeout, this
interrupt can bring the device out of low-power mode. This system setup must meet the conditions
specified in Section 9.3.3, "Low-Power Modes,"
low-power mode.
9-10
Section 9.2.5, "Low-Power Control Register (LPCR),"
Section 9.2.5, "Low-Power Control Register
for the core watchdog interrupt to bring the part out of
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