Freescale Semiconductor MCF54455 Reference Manual page 165

Cache
cmpi.l
bne
rts
The following CACR loads assume: the instruction cache has been invalidated, the default instruction
cache mode is cacheable, the default data cache mode is copyback.
dataCacheLoadAndLock:
move.l #0xa3080800,d0
movec d0,cacr
The following code segments preload half of the data cache (8 Kbytes). It assumes a contiguous block of
data is to be mapped into the data cache, starting at a 0-modulo-8K address.
move.l #512,d0
lea data_,a0
dataCacheLoop:
tst.b (a0)
lea 16(a0),a0
subq.l #1,d0
bne.b dataCacheLoop
; A 8K region has been loaded into ways 0 and 1 of the 16K data cache. lock it!
move.l #0xaa088000,d0
movec d0,cacr
rts
align 16
The following CACR loads assume the data cache has been previously invalidated, the default instruction
cache mode is cacheable, and the default operand cache mode is copyback.
This function must be mapped into a cache-inhibited or SRAM space or these text lines are to be
prefetched into the instruction cache. This may displace some of the 8-Kbyte space being explicitly
fetched.
instructionCacheLoadAndLock:
move.l #0xa2088100,d0
movec d0,cacr
The following code segments preload half of the instruction cache (8 Kbytes). It assumes a contiguous
block of data is to be mapped into the cache, starting at a 0-modulo-8K address
move.l #512,d0
lea code_,a0
instCacheLoop:
intouch (a0)
; Note in the assembler we use, there is no INTOUCH opcode. The following
; is used to produce the required binary representation
cpushl #nc,(a0)
lea 16(a0),a0
subq.l #1,d0
bne.b instCacheLoop
; A 8K region was loaded into levels 0 and 1 of the 16-Kbyte instruction cache. lock it!
move.l #0xa2088800,d0
6-20
#4,d0 ;flushed all the ways?
setloop
; enable and invalidate data cache ...
; ... in the CACR
; 512 16-byte lines in 8K space
; load pointer defining data area
; touch location + load into data cache
; increment address to next line
; decrement loop counter
; if done, then exit, else continue
; set the data cache lock bit ...
; ... in the CACR
; enable and invalidate the instruction
; cache in the CACR
; 512 16-byte lines in 8K space
; load pointer defining code area
; touch location + load into instruction cache
;touch location + load into
;instruction cache
;increment address to next line
;decrement loop counter
;if done, then exit, else continue
;set the instruction cache lock bit
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