Freescale Semiconductor MCF54455 Reference Manual page 811

UART Modules
32.4.1.1 Programmable Divider
As Figure 32-17 shows, the UARTn transmitter and receiver can use the following clock sources:
• An external clock signal on the DTnIN pin.
clock; when divided by 16, it is asynchronous.
• The internal bus clock supplies an asynchronous clock source divided by 32 and then divided by
the 16-bit value programmed in UBG1n and UBG2n. See
Generator Registers
The choice of DTIN or internal bus clock is programmed in the UCSR.
DTnOUT
DTnIN
UnTXD
UnRXD
If DTnIN is a clocking source for the timer or UART, that timer module
cannot use DTnIN for timer input capture.
32.4.1.2 Calculating Baud Rates
The following sections describe how to calculate baud rates.
32.4.1.2.1 Internal Bus Clock Baud Rates
When the internal bus clock is the UART clocking source, it goes through a divide-by-32 prescaler and
then passes through the 16-bit divider of the concatenated UBG1n and UBG2n registers. The baud-rate
calculation is:
Using a 133-MHz internal bus clock and letting baud rate equal 9600, then
Divider
32-17
When not divided,
(UBG1n/UBG2n)."
On-Chip
Timer Module
UART
Clocking sources programmed in UCSR
Tx Buffer
Tx
Rx
Rx Buffer
Figure 32-17. Clocking Source Diagram
NOTE
133MHz

= ------------------------------ - = 433 decimal
 
32 x 9600
DTnIN
Section 32.3.11, "UART Baud Rate
TIN
 1
TIN
 16
16-bit
32
Divider
  
= 0x01B0 hexadecimal
provides a synchronous
Internal
Bus Clock
f
sys/2
Eqn. 32-1
Freescale Semiconductor