Freescale Semiconductor MCF54455 Reference Manual page 491

SDRAM Controller (SDRAMC)
Table 21-1. SDRAM Interface—Detailed Signal Descriptions (continued)
Signal I/O
SD_CAS O Column address strobe/command input. Along with SD_CS, SD_RAS, and SD_WE, defines the current
command.
State
Meaning
Timing
SD_RAS O Row address strobe/command input. Along with SD_CS, SD_CAS, and SD_WE, defines the current
command.
State
Meaning
Timing
SD_CKE O Clock enable. SD_CKE must be maintained high throughout
to put the SDRAM into low-power, self-refresh mode. Input buffers, excluding SD_CLK, SD_CLK, and
SD_CKE, are disabled during self-refresh.
State
Meaning
Timing
SD_CLK O SD_CLK and SD_CLK are differential clock outputs. All address and control output signals are sent on the
SD_CLK crossing of the positive edge of SD_CLK and the negative edge of SD_CLK. Output data is referenced to
the crossing of SD_CLK and SD_CLK (both directions of crossing).
Timing
SD_CS[1:0] O SD_CS provides external bank selection on systems with multiple banks. SD_CS is considered part of the
command code.
State
Meaning
Timing
SD_DATA[31:16] I/O Data bus. In 16-bit DDR configuration, the memory device data bus is connected to SD_D[31:16] bits.
Timing
SD_DQM[3:2] O Output mask signal for write data. During reads, SD_DQM may be driven high, low, or floating. The address
correspondence:
SD_DQM3 - SD_D[31:24]
SD_DQM2 - SD_D[23:16]
State
Meaning
Timing
21-4
See Table 21-10 for the SDRAM commands.
Assertion/Negation — Occurs synchronously with SD_CLK
See Table 21-10 for SDRAM commands.
Assertion/Negation — Occurs synchronously with SD_CLK.
Asserted — Activates internal clock signals and device input buffers and output drivers.
Negated —Deactivates internal clock signals and device input buffers and output drivers.
Assertion — Asynchronous for self-refresh exit and for output disable
Negation — Occurs synchronously with SD_CLK
Command signals occur synchronously with the rising edge of this clock. Data signals can
change on the rising and falling edge of the clock.
Asserted — Commands for the selected chip occur
Negated — All commands are masked.
Assertion/Negation — Occurs synchronously with SD_CLK
Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK.
High Impedance - Depending on the OE_RULE bit in SDCFG1, the SD_DATA bus can be in high
impedance until a write occurs or only when a read occurs.
Asserted — Data is written to SDRAM
Negation — Data is masked
Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK.
Description
and
READ WRITE
accesses. SD_CKE negates
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