Table of Contents
Advertisement
Fast Ethernet Controllers (FEC0 and FEC1)
Field
17–16
Turn around. This field must be programmed to 10 to generate a valid MII management frame.
TA
15–0
Management frame data. This is the field for data to be written to or read from the PHY register.
DATA
To perform a read or write operation on the MII Management Interface, write the MMFRn register. To
generate a valid read or write management frame, ST field must be written with a 01 pattern, and the TA
field must be written with a 10. If other patterns are written to these fields, a frame is generated, but does
not comply with the IEEE 802.3 MII definition.
To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY register),
the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFRn register. Writing this pattern causes
the control logic to shift out the data in the MMFRn register following a preamble generated by the control
state machine. During this time, contents of the MMFRn register are altered as the contents are serially
shifted and are unpredictable if read by the user. After the write management frame operation completes,
the MII interrupt is generated. At this time, contents of the MMFRn register match the original value
written.
To generate an MII management interface read frame (read a PHY register), the user must write {01 10
PHYAD REGAD 10 XXXX} to the MMFRn register (the content of the DATA field is a don't care).
Writing this pattern causes the control logic to shift out the data in the MMFRn register following a
preamble generated by the control state machine. During this time, contents of the MMFRn register are
altered as the contents are serially shifted and are unpredictable if read by the user. After the read
management frame operation completes, the MII interrupt is generated. At this time, the contents of the
MMFRn register match the original value written except for the DATA field whose contents are replaced
by the value read from the PHY register.
If the MMFRn register is written while frame generation is in progress, the frame contents are altered.
Software must use the MII interrupt to avoid writing to the MMFRn register while frame generation is in
progress.
26.4.8
MII Speed Control Registers (MSCR0 & MSCR1)
The MSCRn provides control of the MII clock (FECn_MDC pin) frequency and allows a preamble drop
on the MII management frame.
Address: 0xFC03_0044 (MSCR0)
0xFC03_4044 (MSCR1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS_
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
26-17
Table 26-10. MMFRn Field Descriptions (continued)
Figure 26-8. MII Speed Control Register (MSCRn)
Description
8
Access: User read/write
7
6
5
4
3
2
1
0
0
MII_SPEED
PRE
0
0 0 0 0 0 0 0
Freescale Semiconductor
Advertisement
Table of Contents
