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Address: 0xFC0A_4055 (PCLRR_USB)
7
R
0
W
Reset:
0
Figure 16-33. Port USB Clear Output Data Registers (PCLRR_USB)
Field
PCLRR_x Port x clear data bits.
0 Clears corresponding PODR_x bit
1 No effect
Note: See above figures for bit field positions.
16.3.5
Pin Assignment Registers (PAR_x)
The pin assignment registers control which functions are currently active on the external pins. All pin
assignment registers are read/write.
16.3.5.1
FEC Pin Assignment Register (PAR_FEC)
The PAR_FEC register controls the functions of the FEC0 and FEC1 pins.
Address: 0xFC0A_4060 (PAR_FEC)
7
R
0
W
Reset:
0
Freescale Semiconductor
6
5
4
0
0
0
0
0
0
Table 16-8. PCLRR_x Field Descriptions
Description
6
5
4
PAR_FEC1
0
0
0
Figure 16-34. FEC Pin Assignment (PAR_FEC)
Pin Multiplexing and Control
Access: User write-only
3
2
1
0
0
0
PCLRR_USB
0
0
0
Access: User read/write
3
2
1
0
PAR_FEC0
0
0
0
0
0
0
0
0
16-25
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