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31.4.6.5
Receive FIFO Drain Interrupt or DMA Request (RFDF)
The receive FIFO drain request indicates that the RX FIFO is not empty. The receive FIFO drain request
is generated when the number of entries in the RX FIFO is not zero, and the DSPI_RSER[RFDF_RE] bit
is set. The DSPI_RSER[RFDF_DIRS] bit selects whether a DMA request or an interrupt request is
generated.
31.4.6.6
Receive FIFO Overflow Interrupt Request (RFOF)
The receive FIFO overflow request indicates that an overflow condition in the RX FIFO has occurred. A
receive FIFO overflow request is generated when RX FIFO and shift register are full and a transfer is
initiated. The DSPI_RSER[RFOF_RE] bit must be set for the interrupt request to be generated.
Depending on the state of the DSPI_MCR[ROOE] bit, data from the transfer that generated overflow is
ignored or shifted in to the shift register. If the ROOE bit is set, the incoming data is shifted in to the shift
register. If the ROOE bit is cleared, incoming data is ignored.
31.4.6.7
FIFO Overrun Request (TFUF) or (RFOF)
The FIFO overrun request indicates at least one of the FIFOs in the DSPI has exceeded its capacity. The
FIFO overrun request is generated by logically OR'ing the RX FIFO overflow and TX FIFO underflow
signals.
31.4.7
Power Saving Features
The DSPI supports two power-saving strategies:
•
Module disable mode—clock gating of non-memory mapped logic
•
Clock gating of slave interface signals and clock to memory-mapped logic
31.4.7.1
Module Disable Mode
Module disable mode is a mode the DSPI can enter to save power. Host software can initiate the module
disable mode by setting DSPI_MCR[MDIS]. The MDIS bit is set at reset.
In module disable mode, the DSPI is in a dormant state, but the memory-mapped registers remain
accessible. Certain read or write operations have a different affect when the DSPI is in the module disable
mode. Reading the RX FIFO pop register does not change the state of the RX FIFO. Likewise, writing to
the TX FIFO push register does not change the state of the TX FIFO. Clearing either of the FIFOs does
not have any affect in module disable mode. Changes to the DSPI_MCR[DIS_TXF, DIS_RXF] fields do
not have any affect in module disable mode. In module disable mode, all status bits and register flags in
the DSPI return the correct values when read, but writing to them has no effect. Writing to the DSPI_TCR
during module disable mode does not have any affect. Interrupt and DMA request signals cannot be
cleared while in module disable mode.
31.4.7.2
Slave Interface Signal Gating
The DSPI's module enable signal gates slave interface signals such as address, byte enable, read/write and
data. This prevents toggling slave interface signals from consuming power unless the DSPI is accessed.
Freescale Semiconductor
DMA Serial Peripheral Interface (DSPI)
31-37
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