Freescale Semiconductor MCF54455 Reference Manual page 748

Address: 0xFC07_0003 (DTER0)
0xFC07_4003 (DTER1)
0xFC07_8003 (DTER2)
0xFC07_C003 (DTER3)
7
R 0
W
Reset: 0
Field
7–2 Reserved, must be cleared.
1 Output reference event. The counter value (DTCNn) equals DTRRn. Writing a 1 to REF clears the event condition.
REF Writing a 0 has no effect.
0 Capture event. The counter value has been latched into DTCRn. Writing a 1 to CAP clears the event condition.
CAP Writing a 0 has no effect.
Freescale Semiconductor
6 5
0 0
0 0
Figure 30-4. DTERn Registers
Table 30-4. DTERn Field Descriptions
REF DTMRn[ORRI]
0 X
1 0
1 0
1 1
1 1
DTXMRn
CAP DTMRn[CE]
[DMAEN]
0 XX X
1 00 0
1 00 1
1 01 0
1 01 1
1 10 0
1 10 1
1 11 0
1 11 1
4 3 2
0 0 0
0 0 0
Description
DTXMRn[DMAEN]
X
0 No request asserted
1 No request asserted
0 Interrupt request asserted
1 DMA request asserted
No event
Disable capture event output
Disable capture event output
Capture on rising edge and trigger interrupt
Capture on rising edge and trigger DMA
Capture on falling edge and trigger interrupt
Capture on falling edge and trigger DMA
Capture on any edge and trigger interrupt
Capture on any edge and trigger DMA
DMA Timers (DTIM0–DTIM3)
Access: User read/write
1 0
REF CAP
w1c w1c
0 0
No event
30-6