Freescale Semiconductor MCF54455 Reference Manual page 561

PCI Bus Controller
cache line is fetched internally and only this line returns an error, no data is stored in the PCI controller.
No target abort issues on the PCI bus unless that cache line is requested as a delayed read.
If no byte enables are asserted, the PCI controller completes a read access with all four bytes of valid data.
22.4.4.2 Local Memory Writes
The target interface always posts writes. This allows for data to be latched while waiting for internal access
to local memory. Two 16-byte posted write buffer are implemented to improve data throughput. When
write buffers fill, the target interface keeps the PCI write transaction open on the PCI bus until the buffers
empty enough to transfer more write data or the PCI 16/8 time-out is reached. When write buffers are full,
the target interface negates PCI_TRDY to insert data wait states. If write buffers do not empty some before
16 PCI clocks for the first write beat or 8 PCI clocks for subsequent beats and the PCITCR1[LD] bit is set,
a disconnect issues for the PCI write transaction.
The first buffer simply posts data from the PCI bus and allows for conversion to the faster clock domain.
The second buffer combines data for a potential internal bus burst. When data from the PCI bus aligns to
a 16-byte burst and all byte enables transfer, it is stored in the second buffer. If subsequent PCI beats can
combine with this stored data for a linear burst on the internal bus, all 16-bytes of data store in this buffer
and sent out on the internal bus as a complete 16-byte burst. PCI write data must transfer with all byte
enables enabled (32-bit) to be buffered for a burst on the internal bus, but can be combined from multiple
consecutive PCI write transactions to complete the internal burst. If a target write to a non-sequential
address or a target read occurs before an entire 32-byte burst is buffered, the write data stored transfers on
the internal bus in single beat increments (64 bit, if possible). If partial burst write data (not a complete
16-byte burst) is stored and no new data comes from the PCI bus in a programmed number of PCI cycles,
the buffer times out and sends in single beat. The PCITCR[WCT] field is available to program a timer
value up to 255 PCI cycles. Setting the PCITCR[WCD] bit can also disable the write combine function.
When this bit is set, the second 16-byte buffer is not used. The write combine function does not include
byte packing.
If the PCI controller aborts the transaction in the middle of PCI burst due to internal conflicts, the external
master recognizes some of the data before the abort transfers. However, subsequent transfers of a burst
abort. The external PCI master must query the target abort signalled bit in the PCI Type 00h configuration
status register to determine if a target abort occurred.
22.4.4.3 Data Translation
The internal bus does not support misaligned operations; therefore, it is recommended that software
attempts to transfer contiguous code and data where possible. Non-contiguous transfers degrade
performance. Table 22-32
22-44
and Table 22-33 show PCI-to-internal bus transaction data translation.
Freescale Semiconductor