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Memory Management Unit (MMU)
•
MMUBAR defines a memory-mapped, privileged data-only space with the highest priority in
effective address attribute calculation for the data bus (that is, the MMUBAR has priority over
RAMBAR).
•
If virtual mode is enabled, any normal mode access that does not hit in the MMUBAR, RAMBAR
or ACRs is considered a normal mode virtual address request and generates its access attributes
from the MMU. For this case, the default CACR address attributes are not used.
The MMU also uses TLB contents to perform virtual-to-physical address translation.
4.3.5
MMU Functionality
The MMU provides virtual-to-physical address translation and memory access control. The MMU consists
of memory-mapped, control, status, and fault registers, and a TLB that can be accessed through MMU
registers. Supervisor software can access these resources through MMUBAR. Software can control
address translation and virtual address access attributes by configuring MMU control registers and loading
the MMU's TLB, which functions as a cache, associating virtual addresses to corresponding physical
addresses and providing access attributes. Each TLB entry maps a virtual page. Several page sizes are
supported. Features such as clear-all and probe-for-hit help maintain TLBs.
Fault-free, virtual address accesses that hit in the TLB incur no pipeline delay. Accesses that miss the TLB
or hit the TLB but violate an access attribute generate an access-error exception. On an access error,
software can reference address and information registers in the MMU to retrieve data. Depending on the
fault source, software can obtain and load a new TLB entry, modify the attributes of an existing entry, or
abort the faulting process.
4.3.6
MMU TLB
Each TLB entry consists of two 32-bit fields. The first is the TLB tag entry, and the second is the TLB data
entry. TLB entries can be read and written through MMU registers. TLB contents are unaffected by reset.
4.3.7
MMU Operation
The processor sends instruction-fetch requests and data read/write requests to the MMU internal bus in the
instruction- and operand-address generation cycles (IAG and OAG). The processor local bus controller
and memories occupy the next two pipeline stages, instruction fetch cycles 1 and 2 (IC1 and IC2) and
operand fetch cycles 1 and 2 (OC1 and OC2). For late writes, optional data pipeline stages are added to
the processor local bus controller as well as any writable memories.
Table 4-12
shows the association between internal memory pipeline stages and the processor's pipeline
structures
(Figure
4-1).
.
Table 4-12. Version 4 Processor Local Bus Memory Pipelines
Processor Local Bus Memory Pipeline Stage
J stage
KC1 stage
4-18
Instruction Fetch Pipeline Operand Execution Pipeline
IAG
IC1
OAG
OC1
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