Flexbus Signals - Freescale Semiconductor MCF54455 Reference Manual

2.3.4

FlexBus Signals

Table 2-6 describes signals that are used for performing transactions on the external bus.
Signal Name
Address/Data Bus FB_AD[31:0]
Byte Enables FB_BE/BWE[3:0] Defines flow of data on data bus. During peripheral accesses, these
Output Enable FB_OE
Transfer Acknowledge FB_TA
Read/Write FB_R/W
Transfer Size FB_TSIZ[1:0]
Transfer Burst FB_TBST
Transfer Start FB_TS
Address Latch Enable FB_ALE
Chip Selects FB_CS[3:0]
Freescale Semiconductor
Table 2-6. FlexBus Signals
Abbreviation
Defines address and data of external byte, word, and longword
accesses. This three-state, bi-directional bus is the general-purpose
address/data path to external SRAM and flash devices.
output signals indicate that data is to be latched or driven onto a byte
of the data bus when driven low. The BE/BWE[3:0] signals are
asserted only to the memory bytes used during a read or write access.
BE/BWE0 controls access to the most significant byte lane of data,
and BE/BWE3 controls access to the least significant byte lane of
data.
For SRAM or Flash devices, the BE/BWEn outputs should be
connected to individual byte strobe signals.
The BE/BWEn signals are asserted during accesses to on-chip
peripherals, but not to on-chip SRAM or cache.
Indicates when an external device can drive data during external read
cycles.
Indicates external data transfer is complete. During a read cycle, when
the processor recognizes TA, it latches the data and then terminates
the bus cycle. During a write cycle, when the processor recognizes TA,
the bus cycle is terminated.
Indicates direction of the data transfer on the bus for SRAM (R/W)
accesses. A logic 1 indicates a read from a slave device and a logic 0
indicates a write to a slave device.
Indicates bus width (8, 16, or 32 bits) for each chip select. The initial
width for the bootstrap program chip select is determined by the initial
state of TSIZ[1:0].
Indicates external bus access is a burst access.
Bus control output signal indicating the start of a transfer.
Indicates device has begun a bus transaction and the address and
attributes are valid. FB_ALE is asserted for one bus clock cycle. In
multiplexed mode, ALE is used externally as an address latch enable
to capture the address phase of the bus transfer.
Select external devices for external bus transactions.
Function
Signal Descriptions
I/O
I/O
O
O
I
O
O
O
O
O
O
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