Freescale Semiconductor MCF54455 Reference Manual page 230

Field
2 Port change detect. This bit is not EHCI compatible.
PCI Host mode:
Controller sets this bit when a connect status occurs on any port, a port enable/disable change occurs, an
over-current change occurs, or the force port resume (PORTSCn[FPR]) bit is set as the result of a J-K
transition on the suspended port.
Device mode:
The controller sets this bit when it enters the full- or high-speed operational state. When it exits the full- or
high-speed operation states due to reset or suspend events, the notification mechanisms are URI and bits
respectively. The device controller detects resume signaling only.
1 USB error interrupt. When completion of USB transaction results in error condition, the controller sets this bit.
UEI If the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set, this bit is set
along with the USBINT bit. See Section 4.15.1 in the EHCI specification for a complete list of host error interrupt
conditions. See
0 No error.
1 Error detected.
0 USB interrupt (USBINT). This bit is set by the controller when the cause of an interrupt is a completion of a USB
UI transaction where the TD has an interrupt on complete (IOC) bit set. This bit is also set by the controller when
a short packet is detected. A short packet is when the actual number of bytes received was less than the
expected number of bytes.
10.3.4.3 USB Interrupt Enable Register (USBINTR)
The interrupts to software are enabled with this register. An interrupt generates when a bit is set and the
corresponding interrupt is active. The USB status register (USBSTS) continues to show interrupt sources
(even if the USBINTR register disables them), allowing polling of interrupt events by the software.
Address: 0xFC0B_0148 (USBINTR)
31 30 29
R 0 0 0
W
Reset 0 0 0
15 14 13
R 0 0 0
W
Reset 0 0 0
Freescale Semiconductor
Table 10-20. USBSTS Field Descriptions (continued)
Table 10-58 for more information on device error matrix.
28 27 26 25
0 0 0
TIE1
0 0 0 0
12 11 10 9
0 0 0
ULPIE
0 0 0 0
Figure 10-19. USB Interrupt Enable Register (USBINTR)
Universal Serial Bus Interface – On-The-Go Module
Description
24 23 22 21
0 0 0
TIE0
0 0 0 0
8 7 6 5
SLE SRE URE AAE
0 0 0 0
Access: User read/write
20 19 18 17
0 0
UPIE UAIE NAKE
0 0 0 0
4 3 2 1
SEE FRE PCE UEE
0 0 0 0
10-23
16
0
0
UE
0