Freescale Semiconductor MCF54455 Reference Manual page 610

24.3.3.18 DES Key Setup (
cp0ld.l #DESK+{CP}+{DC}
The command performs the initial key transformation (permuted choice 1) defined by the DES
DESK
algorithm on CA0 and CA1 with CA0 containing bits 1–32 of the key and CA1 containing bits 33–64 of
1
the key . If the DC bit is set, no shift operation performs and the values C
CA1 respectively. The DC bit should be set for decrypt operations. If the DC bit is not set, a left shift by
one also occurs and the values C
cleared for encrypt operations. If the CP bit is set and a key parity error is detected, CASR[DPE] bit is set;
otherwise, it is cleared.
24.3.3.19 Hash Function (
cp0ld.l #HASH+HFx
The command performs a hashing operation on a set of registers and adds that result to the value in
HASH
CAA and stores the result in CAA. The specific hash function performed is based on the HFx field as
defined in Table 24-10.
HFx
Code Define
0 HFF
1 HFG
2 HFH
3
4 HFC
5 HFM
24.3.3.20 Secure Hash Shift (
cp0ld.l #SHS
The command does a set of parallel register-to-register move and shift operations for implementing
SHS
SHA-1. The following source and destination assignments are made: CAA=CAA<<<5, CA0=CAA,
CA1=CA0, CA2=CA1<<<30, CA3=CA2, CA4=CA3.
1.The DES algorithm numbers the most significant bit of a block as bit 1 and the least significant as bit 64.
Freescale Semiconductor
Table 24-9. Key Shift Function Codes (continued)
KSx KSx
Code Define
2 KSR1
3 KSR2
)
DESK
and D store back to CA0 and CA1 respectively. The DC bit should be
1 1
)
HASH
Table 24-10. Hash Function Codes
HFx
Hash Function
MD5 F()
MD5 G()
MD5 H(), SHA Parity()
HFI MD5 I()
SHA Ch()
SHA Maj()
)
SHS
Cryptographic Acceleration Unit (CAU)
Shift Function
Right 1
Right 2
and D
0
Hash Logic
(CA1 & CA2) | (CA1 & CA3)
(CA1 & CA3) | (CA2 & CA3)
CA1 ^ CA2 ^ CA3
CA2 ^ (CA1 | CA3)
(CA1 & CA2) ^ (CA1 & CA3)
(CA1 & CA2) ^ (CA1 & CA3) ^ (CA2 & CA3)
store back to CA0 and
0
24-10