Freescale Semiconductor MCF54455 Reference Manual page 764

Field
26 Clock polarity. Selects the inactive state of the serial communications clock (DSPI_SCK). This bit is used in master
CPOL and slave mode. For successful communication between serial devices, the devices must have identical clock
polarities. When the continuous selection format is selected (CONT or DCONT is set), switching between clock
polarities without stopping the DSPI can cause errors in the transfer due to the peripheral device interpreting the
switch of clock polarity as a valid clock edge. For more information on continuous selection format, refer to
Section 31.4.4.5, "Continuous Selection
0 The inactive state value of DSPI_SCK is low
1 The inactive state value of DSPI_SCK is high
25 Clock phase. Selects which edge of DSPI_SCK causes data to change and which edge causes data to be captured.
CPHA This bit is used in master and slave mode. For successful communication between serial devices, the devices must
have identical clock phase settings.
Note: When the continuous selection format is selected (CONT or DCONT is set), switching between clock phases
without stopping the DSPI can cause errors in the transfer.
0 Data is captured on the leading edge of DSPI_SCK and changed on the following edge
1 Data is changed on the leading edge of DSPI_SCK and captured on the following edge
24 LSB first enable. Selects if the LSB or MSB of the frame is transferred first. This bit is only used in master mode.
LSBFE 0 Data is transferred MSB first
1 Data is transferred LSB first
23–22 PCS to SCK delay prescaler. Selects the prescaler value for the delay between assertion of DSPI_PCS and the first
PCSSCK edge of the DSPI_SCK. This field is only used in master mode.
Note: When the continuous selection format is selected (CONT or DCONT is set), switching the PCS to SCK delay
prescaler without stopping the DSPI can cause errors in the transfer.
Note: See Section 31.4.3.2, "PCS to SCK Delay
00 1 clock DSPI_PCS to DSPI_SCK delay prescaler
01 3 clock DSPI_PCS to DSPI_SCK delay prescaler
10 5 clock DSPI_PCS to DSPI_SCK delay prescaler
11 7 clock DSPI_PCS to DSPI_SCK delay prescaler
21–20 After SCK delay prescaler. Selects the prescaler value for the delay between the last edge of DSPI_SCK and the
PASC negation of DSPI_PCS. This field is only used in master mode. The ASC field description in
to compute the after SCK delay.
00 1 clock delay between last edge of DSPI_SCK and DSPI_PCS negation prescaler
01 3 clock delay between last edge of DSPI_SCK and DSPI_PCS negation prescaler
10 5 clock delay between last edge of DSPI_SCK and DSPI_PCS negation prescaler
11 7 clock delay between last edge of DSPI_SCK and DSPI_PCS negation prescaler
19–18 Delay after transfer prescaler. The PDT field selects the prescaler value for the delay between the negation of the
PDT DSPI_PCS signal at the end of a frame and the assertion of DSPI_PCS at the beginning of the next frame. The PDT
field is only used in master mode. The DT field description in
transfer.
00 1 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler
01 3 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler
10 5 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler
11 7 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler
Freescale Semiconductor
Table 31-5. DSPI_CTARn Field Description (continued)
Format."
Description
(tCSC)," for details on calculating the PCS to SCK delay.
Table 31-5 explains how to compute the delay after
DMA Serial Peripheral Interface (DSPI)
Table 31-5 explains how
31-11