Freescale Semiconductor MCF54455 Reference Manual page 818

Although slave stations have their receivers disabled, they continuously monitor the master's data stream.
When the master sends an address character, the slave receiver notifies its respective CPU by setting
USRn[RXRDY] and generating an interrupt (if programmed to do so). Each slave station CPU then
compares the received address to its station address and enables its receiver if it wishes to receive the
subsequent data characters or block of data from the master station. Unaddressed slave stations continue
monitoring the data stream. Data fields in the data stream are separated by an address character. After a
slave receives a block of data, its CPU disables the receiver and repeats the process. Functional timing
information for multidrop mode is shown in
UnTXD
Transmitter
Enabled
USRn[TXRDY]
internal
module
select
UMR1n[PM] = 11
UMR1n[PT] = 1
UnRXD
Receiver
Enabled
USRn[RXRDY]
internal
module
select
UMR1
A character sent from the master station consists of a start bit, a programmed number of data bits, an
address/data (A/D) bit flag, and a programmed number of stop bits. A/D equals 1 indicates an address
character; A/D equals 0 indicates a data character. The polarity of A/D is selected through UMR1n[PT].
UMR1n should be programmed before enabling the transmitter and loading the corresponding data bits
into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it
is enabled or disabled. If the receiver is disabled, it sets the RXRDY bit and loads the character into the
receiver holding register FIFO provided the received A/D bit is a 1 (address tag). The character is
Freescale Semiconductor
Figure
Master Station
A/D
ADD1 1 C0
ADD 1 C0
UMR1n[PT] = 0
Peripheral Station
A/D A/D
0 ADD1 1 C0
n
[PM] = 11 ADD 1
Figure 32-24. Multidrop Mode Timing Diagram
32-24.
A/D
ADD 2
UMR1n[PT] = 1
A/D
Status Data
(C0)
UART Modules
A/D
ADD2 1
A/D A/D
ADD2 1 0
Status Data
(ADD 2)
32-24