Freescale Semiconductor MCF54455 Reference Manual page 546

22.4.1.2 Basic Transfer Control
The basic PCI bus transfer mechanism is a burst. A burst is an address phase followed by one or more data
phases. Fundamentally, all PCI data transfers are controlled by three signals: PCI_FRAME, PCI_IRDY,
and PCI_TRDY. An initiator asserts PCI_FRAME begin a PCI bus transaction and negates PCI_FRAME
to end a PCI bus transaction. An initiator negates PCI_IRDY to force wait cycles, while a target negates
PCI_TRDY to force wait cycles.
The PCI bus is considered idle when PCI_FRAME and PCI_IRDY are negated. The first clock cycle in
which PCI_FRAME asserts indicates the beginning of the address phase. The address and bus command
code transfer in that first cycle. The next cycle begins the first of one or more data phases. Data transfers
between initiator and target in each cycle that PCI_IRDY and PCI_TRDY assert. The initiator (by negating
PCI_IRDY) or target (by negating PCI_TRDY) may insert wait cycles in a data phase.
After an initiator asserts PCI_IRDY, it cannot change PCI_IRDY or PCI_FRAME until the current data
phase completes, regardless of the state of PCI_TRDY. After a target asserts PCI_TRDY or PCI_STOP, it
cannot change PCI_DEVSEL, PCI_TRDY, or PCI_STOP until the current data phase completes. In
simpler terms, after an initiator or target has committed to the data transfer, it cannot back out.
When the initiator intends to complete only one more data transfer (which can happen immediately after
the address phase), PCI_FRAME negates and PCI_IRDY asserts (or kept asserted) indicating the initiator
is ready. After the target indicates the final data transfer (by asserting PCI_TRDY), the PCI bus may return
to the idle state (PCI_FRAME and PCI_IRDY are negated) unless a fast back-to-back transaction is in
progress. In the case of a fast back-to-back transaction, an address phase immediately follows the last
phase.
22.4.1.3 PCI Transactions
The figures in this section show the basic
Figure 22-35 shows a PCI burst read transaction (2-beat). The signal PCI_FRAME is driven low to initiate
the transfer. Cycle 1 is the address phase with valid address information driven on the AD bus and a PCI
command driven on the PCI_CBE bus. In cycle 2, the AD bus is in a turnaround cycle because of the read
on a muxed bus. The byte enables, which are active low, are driven onto the PCI_CBE bus in this clock.
Any combination of byte enables can be asserted (none may be asserted individually). A target responds
to an address phase by driving the PCI_DEVSEL signal. The specification allows for four types of decode
operations. The target can drive PCI_DEVSEL in 1, 2, or 3 clocks depending on whether the target is a
fast, medium, or slow decode device, respectively. A single device can drive PCI_DEVSEL if no other
agent responds by the fourth clock. This is called subtractive decoding in PCI terminology. The this PCI
controller is a medium target decode device.
A valid transfer occurs when PCI_IRDY and PCI_TRDY are asserted. If either are negated during a data
phase, it is considered a wait state. The target asserts a wait state in cycles 3 and 5 of
master indicates the final data phase is to occur by negating PCI_FRAME. In
responds as a medium device, driving PCI_DEVSEL in cycle 3.
The final data phase occurs in cycle 6. Another agent cannot start an access until cycle 8. A provision in
the specification allows the current master to start another transfer in cycle 7 when certain conditions
apply. Refer to fast back-to-back transfers in the PCI specification for more details.
Freescale Semiconductor
and
MEMORY READ MEMORY WRITE
PCI Bus Controller
command transactions.
Figure 22-35. A
Figure 22-35, the target
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