Freescale Semiconductor MCF54455 Reference Manual page 227

Universal Serial Bus Interface – On-The-Go Module
Field
1 Controller reset. Software uses this bit to reset controller. Controller clears this bit when reset process
RST completes. Clearing this register does not allow software to terminate the reset process early.
Host mode:
When software sets this bit, the controller resets its internal pipelines, timers, counters, state machines etc.
to their initial value. Any transaction in progress on the USB immediately terminates. A USB reset is not
driven on downstream ports. Software must not set this bit when the USBSTS[HCH] bit is cleared.
Attempting to reset an actively running host controller results in undefined behavior.
Device mode:
When software sets this bit, the controller resets its internal pipelines, timers, counters, state machines, etc.
to their initial value. Setting this bit with the device in the attached state is not recommended because it has
an undefined effect on an attached host. To ensure the device is not in an attached state before initiating a
device controller reset, all primed endpoints must be flushed and the USBCMD[RS] bit must be cleared.
0 Run/Stop.
RS Host mode:
When set, the controller proceeds with the execution of the schedule. The controller continues execution as
long as this bit is set. When this bit is cleared, the controller completes the current transaction on the USB
and then halts. The USBSTS[HCH] bit indicates when the host controller finishes the transaction and enters
the stopped state. Software must not set this bit unless controller is in halted state (USBSTS[HCH] = 1).
Device mode:
Setting this bit causes the controller to enable a pull-up on DP and initiate an attach event. This control bit is
not directly connected to the pull-up enable, as the pull-up becomes disabled upon transitioning into
high-speed mode. Software must use this bit to prevent an attach event before the USB OTG controller has
properly initialized. Clearing this bit causes a detach event.
10.3.4.2 USB Status Register (USBSTS)
This register indicates various states of each module and any pending interrupts. This register does not
indicate status resulting from a transaction on the serial bus. Software clears certain bits in this register by
writing a 1 to them.
Address: 0xFC0B_0144 (USBSTS)
31 30 29
R 0 0 0
W
Reset 0 0 0
15 14 13
R AS PS RCL
W
Reset 0 0 0
10-20
Table 10-19. USBCMD Field Descriptions (continued)
28 27 26 25
0 0 0 TI1
w1c
0 0 0 0
12 11 10 9
HCH 0 ULPII 0
0 0 0 0
Figure 10-18. USB Status Register (USBSTS)
Description
24 23 22 21
TI0 0 0 0
w1c
0 0 0 0
8 7 6 5
SRI URI AAI
w1c w1c w1c w1c
0 1 0 0
Access: User read/write
20 19 18 17
0 0 NAKI
UPI UAI
0 0 0 0
4 3 2 1
SEI FRI PCI UEI
w1c w1c w1c w1c
0 0 0 0
Freescale Semiconductor
16
0
0
UI
w1c
0