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21.4.2
SDRAM Control Register (SDCR)
The SDCR
(Figure
21-5) controls SDRAMC operating modes, including refresh count and address line
muxing.
Address: 0xFC0B_8004 (SDCR)
31
30
29
R MODE
DDR_
CKE
_EN
MODE
W
Reset
0
0
0
15
14
13
R
0
0
MEM_
PS
W
Reset
0
0
1
Field
31
SDRAM mode register programming enable.
MODE_EN
0 SDMR locked, cannot be written.
1 SDMR enabled, can be written.
Note: MODE_EN must be cleared during normal operation,
30
Clock enable. CKE must be set to perform normal read and write operations. Clear CKE to put the memory in
CKE
self-refresh or power-down mode.
0 SD_CKE is negated (low)
1 SD_CKE is asserted (high)
29
DDR mode select.
DDR_MODE
Reserved
1 DDR mode
28
Refresh enable.
REF_EN
0 Automatic refresh disabled
1 Automatic refresh enabled
27
DDR2 mode select.
DDR2_MODE
0 DDR mode
1 DDR2 mode
Note: If DDR_MODE is cleared, this bit is ignored.
26
Reserved, must be cleared.
25–24
Controls the use of internal address bits A[27:24] as row or column bits on the SD_A bus. See
ADDR_MUX
Table
21-3.
23
Reserved, must be cleared.
22
Drive rule selection.
OE_RULE
0 Tri-state except to write. SD_D and SD_DQS are only driven when necessary to perform a write command.
1 Drive except to read. SD_D and SD_DQS are only tristated when necessary to perform a read command.
When not being driven for a write cycle, SD_D hold the most recent value and SD_DQS are driven low. This
mode is intended for minimal applications only, to prevent floating signals and allow unterminated board
traces. However, terminated wiring is always recommended over unterminated.
Freescale Semiconductor
28
27
26
25
0
REF_
DDR2_
ADDR_MUX
EN
MODE
0
0
0
0
12
11
10
9
0
0
DQS_OE
0
0
0
0
Figure 21-5. SDRAM Control Register (SDCR)
Table 21-6. SDCR Field Descriptions
24
23
22
21
0
OE_
RULE
0
0
0
0
8
7
6
5
0
0
0
0
0
0
0
0
Description
SDRAM Controller (SDRAMC)
Access: User read/write
20
19
18
17
REF_CNT
0
0
0
0
4
3
2
1
0
0
0
0
DPD
IREF IPALL
0
0
0
0
Table
21-2, and
21-11
16
0
0
0
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