Freescale Semiconductor MCF54455 Reference Manual page 564

A LRU priority scheme allows for fairness in priority resolution because no one master can prevent other
masters from gaining access to the bus. The priority level, high or low, provides a simple weighting
mechanism for master access to the bus.
Priority in a LRU scheme adjusts so that the last master serviced assigns the lowest priority in its level.
Masters with lower priority shift to the next higher priority position. The PCI controller is positioned
before all external devices in priority. If a master does not requesting the bus, its transaction slot is given
to the next requesting device within its priority group.
During hidden arbitration, PCI_GNT given to a requesting master while the PCI bus is active may be
removed and awarded to a higher priority device if a higher priority device asserts its request. If the bus is
idle when a device requests the bus, the arbiter deasserts the currently asserted PCI_GNT for one PCI clock
cycle. The arbiter evaluates the priorities of all requesting devices and grants the bus to the highest priority
device in the next cycle.
Figure 22-41 shows the initial state of the arbitration algorithm. Two devices are assigned high-priority
(the internal and one external master) and four low-priority. If all masters request the use of the PCI bus
continuously, the PCI_GNT sequence is:
1. PCI controller, device 1, device 0,
2. PCI controller, device 1, device 2,
3. PCI controller, device 1, device 3,
4. Goto step 1.
If device 1 is not requesting the bus, the PCI_GNT sequence is:
1. PCI controller, device 0,
2. PCI controller, device 2,
3. PCI controller, device 3,
4. Goto step 1.
If, after this sequence completes, all devices request the bus (including now device 1), the arbiter assigns
PCI_GNT to device 1 because it is the longest since device 1 used the bus (it has highest priority). After
all requests are serviced, the priority resets to the initial state.
Freescale Semiconductor
PCI Bus Controller
22-47