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4.3.8.2
TLB Replacement Algorithm
The instruction and data TLBs provide low-latency access to recently used instruction and operand
translation information. The ITLBs and DTLBs are 32-entry fully associative caches. The 32 ITLB entries
are searched on each instruction reference; the 32 DTLB entries are searched on each operand reference.
The TLBs are software controlled. The TLB clear-all function clears valid bits on every TLB entry and
resets the replacement logic. A new valid entry loaded in the TLBs may be designated as locked and
unavailable for allocation. TLB hits to locked entries do not update replacement algorithm information.
When a new TLB entry needs to be allocated, the user can specify the exact TLB entry to be updated
(through MMUOR[ADR] and MMUAR) or let TLB hardware pick the entry to update based on the
replacement algorithm. A pseudo least recently used (PLRU) algorithm picks the entry to replace on a TLB
miss. The algorithm works as follows:
•
If any element is empty (non-valid), use the lowest empty element as the allocate entry (entry 0
before 1, 2, 3, and so on).
•
If all entries are valid, use the entry indicated by the PLRU as the allocate entry.
The PLRU algorithm uses 31 most recently used state bits per TLB to track the TLB hit history.
lists these state bits.
rdRecent31To16
rdRecent31To24
rdRecent15To08
rdRecent31To28
rdRecent23To20
rdRecent15To12
rdRecent07To04
rdRecent31To30
rdRecent27To26
rdRecent23To22
rdRecent19To18
rdRecent15To14
rdRecent11To10
rdRecent07To06
rdRecent03To02
Freescale Semiconductor
Table 4-14. PLRU State Bits
State Bits
A 1 indicates 31To16 is more recent than 15To00
A 1 indicates 31To24 is more recent than 23To16
A 1 indicates 15To08 is more recent than 07To00
A 1 indicates 31To28 is more recent than 27To24
A 1 indicates 23To20 is more recent than 19To16
A 1 indicates 15To12 is more recent than 11To08
A 1 indicates 07To04 is more recent than 03To00
A 1 indicates 31To30 is more recent than 29To28
A 1 indicates 27To26 is more recent than 25To24
A 1 indicates 23To22 is more recent than 21To20
A 1 indicates 19To18 is more recent than 17To16
A 1 indicates 15To14 is more recent than 13To12
A 1 indicates 11To10 is more recent than 09To08
A 1 indicates 07To06 is more recent than 05To04
A 1 indicates 03To02 is more recent than 01To00
rdRecent31
A 1 indicates 31 is more recent than 30
rdRecent29
A 1 indicates 29 is more recent than 28
rdRecent27
A 1 indicates 27 is more recent than 26
Memory Management Unit (MMU)
Meaning
Table 4-14
4-21
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