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Field
1
Write protect. Determines whether the peripheral allows write accesses
WP
0 This peripheral allows write accesses.
1 This peripheral is write protected. If a write access is attempted, access terminates with an error response and
no peripheral access initiates.
0
Trusted protect. Determines whether the peripheral allows accesses from an untrusted master.
TP
0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access
terminates with an error response and no peripheral access initiates.
14.2.3
Core Watchdog Control Register (CWCR)
The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer
interrupt. The register can be read or written at any time. At system reset, the software watchdog timer is
disabled.
Address: 0xFC04_0016 (CWCR)
15
14
13
R
0
0
RO
W
Reset
0
0
0
Field
15
Read-only control bit.
RO
0 CWCR can be read or written.
1 CWCR is read-only. A system reset is required to clear this register. The setting of this bit is intended to prevent
accidental writes of the CWCR from changing the defined core watchdog configuration.
14–9
Reserved, must be cleared.
8
Core watchdog run while halted.
CWRWH
0 Core watchdog timer stops counting if the core is halted.
1 Core watchdog timer continues to count even while the core is halted.
7
Core watchdog timer enable.
CWE
0 CWT is disabled.
1 CWT is enabled.
Freescale Semiconductor
Table 14-5. PACRn Field Descriptions (continued)
12
11
10
9
0
0
0
0
0
0
0
0
Figure 14-11. Core Watchdog Control Register (CWCR)
Table 14-6. CWCR Field Descriptions
Description
8
7
6
5
CW
CWE
CWRI
RWH
0
0
0
0
Description
System Control Module (SCM)
Access: User read/write
4
3
2
1
CWT
0
0
0
0
14-7
0
0
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