Freescale Semiconductor DSP56374 Manuals

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Freescale Semiconductor DSP56374 User Manual (258 pages)

24-bit digital signal

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 4.46 MB

Table of Contents
3
List of Tables
15
Revision History
19
Manual Conventions
20
Chapter 1 DSP56374 Overview

21
- Introduction
  21
- DSP56300 Core Description
  22
- DSP56374 Audio Processor Architecture
  23
- DSP56300 Core Functional Blocks
  23
- Data ALU
  23
- Data ALU Registers
  23
- Multiplier-Accumulator (MAC)
  23
- Address Generation Unit (AGU)
  24
- Program Control Unit (PCU)
  24
- Internal Buses
  24
- Direct Memory Access (DMA)
  25
- PLL-Based Clock Oscillator
  25
- On-Chip Memory
  25
- Off-Chip Memory Expansion
  25
- Power Requirements
  25
- Peripheral Overview
  26
- General Purpose Input/Output (GPIO)
  26
- Triple Timer (TEC)
  26
- Enhanced Serial Audio Interface (ESAI)
  27
- Enhanced Serial Audio Interface 1 (ESAI_1)
  27
- Serial Host Interface (SHI)
  27
- Watchdog Timer (WDT)
  27
Chapter 2 Signal/Connection Descriptions

29
- Signal Groupings
  29
- Power
  29
- Pin VDD Connections
  30
- Ground
  31
- Scan
  32
- Clock and PLL
  32
- Interrupt and Mode Control
  32
- Serial Host Interface
  34
- Enhanced Serial Audio Interface
  36
- Enhanced Serial Audio Interface_1
  40
- Dedicated GPIO - Port G
  44
- Timer
  46
- Jtag/Once Interface
  47
Chapter 3 Memory Configuration

49
- Data and Program Memory Maps
  49
- Default Memory Map (MS 0)
  50
- Memory Map (MS 1, MSW(1-0) 10)
  51
- Memory Map (MS 1, MSW(1-0) 01)
  52
- Reserved Memory Spaces
  53
- Bootstrap CODE
  53
- Dynamic Memory Configuration Switching
  53
- External Memory Support
  53
- DMA and Memory
  53
- Memory BLOCKS
  54
- Memory Patch Module
  54
- Internal I/O Memory Map
  55
Chapter 4 Core Configuration

57
- Introduction
  57
- Operating Mode Register (OMR)
  57
- RESERVED - Bits 4, 5, 10 - 15 and 23
  57
- Operating Modes
  57
- Interrupt Priority Registers
  59
- DMA Request Sources
  60
- PLL Initialization
  61
- PLL Pre-Divider Factor (PD0-PD4)
  62
- PLL Multiplication Factor (MF0-MF7)
  62
- PLL Feedback Multiplier (OD1)
  62
- PLL Output Divide Factor (OD0-OD1)
  62
- PLL Divider Factor (DF0-DF2)
  62
- Pll Lock Mux (Plkm)
  62
- Device Identification (ID) Register
  62
- JTAG Identification (ID) Register
  62
Chapter 5 PLL and Clock Generator

65
- Introduction
  65
- PLL and Clock Signals
  65
- PLL Block
  65
- Frequency Predivider
  66
- Phase Detector and Charge Pump Loop Filter
  66
- Voltage Controlled Oscillator (VCO)
  66
- PLL Dividers
  66
- PLL Multiplication Factor (MF)
  67
- PLL Operation
  67
- EXTAL Clock Input Division
  67
- PLL Frequency Multiplication
  67
- PLL Output Frequency (PLL Out)
  68
- PLL out = VCO Out/2 [OD1 = 0, OD0 = 1]
  69
- Clock Generator
  70
- Low-Power Divider (LPD)
  70
- Operating Frequency (Fosc)
  70
- PLL Programming Model
  71
- PLL Initialization Procedure
  74
- PLL Programming Examples
  75
Chapter 6 General Purpose Input/Output

77
- Introduction
  77
- Programming Model
  77
- Port C and E Signals and Registers
  77
- Port G Signals and Registers
  77
- Port G Control Register (PCRG)
  77
- Port G Direction Register (PRRG)
  77
- Port G Data Register (PDRG)
  78
- ESAI/EXTAL Clocking Control
  78
- Port H Signals and Registers
  79
- Port H Control Register (PCRH)
  79
- Port H Direction Register (PRRH)
  79
- Port H Data Register (PDRH)
  80
- Timer/Event Counter Signals
  81
Chapter 7 Serial Host Interface

83
Chapter 8 Enhanced Serial Audio Interface (ESAI)

101
Chapter 9

141
- Overview
  141
- Triple Timer Module Block Diagram
  141
- Individual Timer Block Diagram
  141
- Operation
  142
- Timer after Reset
  142
- Timer Initialization
  142
- Timer Exceptions
  143
- Operating Modes
  143
- Triple Timer Modes
  143
- Timer GPIO (Mode 0)
  144
- Timer Pulse (Mode 1)
  145
- Pulse Mode (TRM = 1)
  146
- Timer Toggle (Mode 2)
  147
- Toggle Mode, TRM = 1
  148
- Timer Event Counter (Mode 3)
  149
- Signal Measurement Modes
  150
- Measurement Input Width (Mode 4)
  150
- Pulse Width Measurement Mode, TRM = 1
  151
- Measurement Input Period (Mode 5)
  152
- Measurement Capture (Mode 6)
  153
- Pulse Width Modulation (PWM, Mode 7)
  154
- Pulse Width Modulation Toggle Mode, TRM = 1
  155
- Watchdog Modes
  156
- Watchdog Pulse (Mode 9)
  156
- Watchdog Toggle (Mode 10)
  157
- Reserved Modes
  158
- Special Cases
  158
- DMA Trigger
  158
- Triple Timer Module Programming Model
  158
- Prescaler Counter
  158
- Timer Prescaler Load Register (TPLR)
  159
- Timer Prescaler Count Register (TPCR)
  160
- Timer Control/Status Register (TCSR)
  161
- Timer Load Register (TLR)
  165
- Timer Compare Register (TCPR)
  165
- Timer Count Register (TCR)
  165
Chapter 10 Watchdog Timer Module

167
- Introduction
  167
- WDT Pin
  167
- WDT Operation
  167
- Description of Registers
  168
- Watchdog Control Register (WCR)
  168
- Watchdog Counter & WCNTR Register
  169
- Watchdog Modulus Register (WMR)
  169
- Watchdog Service Register (WSR)
  170
- Operation in Different Modes
  170
- WAIT Mode
  170
- DEBUG Mode
  170
- Stop Mode
  170
Appendix A Bootstrap Source Code

171
- DSP56374 Bootstrap Program
  171
- Using the Serial EEPROM Boot Mode
  175
Appendix B Equates

185
Appendix C Programmer's Reference

203
- Introduction
  203
- Peripheral Addresses
  203
- Interrupt Addresses
  203
- Interrupt Priorities
  203
- Programming Sheets
  203
- Internal I/O Memory Map
  203
- Interrupt Vector Addresses
  209
- Interrupt Source Priorities (Within an IPL
  212
- Programming Sheets
  213
Appendix Dbsdl

243
- 52-Pin BSDL
  243
- 80-Pin BSDL
  248

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Freescale Semiconductor DSP56374 Manuals

Freescale Semiconductor DSP56374 User Manual (258 pages)

Table of Contents

Chapter 1 DSP56374 Overview

Chapter 2 Signal/Connection Descriptions

Chapter 3 Memory Configuration

Chapter 4 Core Configuration

Chapter 5 PLL and Clock Generator

Chapter 6 General Purpose Input/Output

Chapter 7 Serial Host Interface

Chapter 8 Enhanced Serial Audio Interface (ESAI)

Chapter 9

Chapter 10 Watchdog Timer Module

Appendix A Bootstrap Source Code

Appendix B Equates

Appendix C Programmer's Reference

Appendix Dbsdl

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