Freescale Semiconductor MCF54455 Reference Manual page 703

Synchronous Serial Interface (SSI)
3. Write data to transmit data register (SSI_TX0)
4. Transmitter enabled (TE = 1)
5. Frame sync active (for continuous clock case)
6. Bit clock begins (for gated clock case)
When the above conditions occur in normal mode, the next data word transfers into the transmit shift
register (TXSR) from the transmit data register 0 (SSI_TX0) or from the transmit FIFO 0 register, if
enabled. The new data word transmits immediately.
If transmit FIFO 0 is not enabled and the transmit data register empty (TDE0) bit is set, a transmit
interrupt 0 occurs if the TIE and SSI_IER[TDE0] bits are set.
If transmit FIFO 0 is enabled and the transmit FIFO empty (TFE0) bit is set, transmit interrupt 0 occurs if
the TIE and SSI_IER[TFE0] bits are set. If transmit FIFO 0 is enabled and filled with data, eight data
words can be transferred before the core must write new data to the SSI_TX0 register.
The SSI_TXD port is disabled except during the data transmission period. For a continuous clock, the
optional frame sync output and clock outputs are not disabled, even if receiver and transmitter are disabled.
27.4.1.1.2 Normal Mode Receive
Conditions for data reception from the SSI are:
1. SSI enabled (SSI_CR[SSI_EN] = 1)
2. Enable receive FIFO (optional)
3. Receiver enabled (RE = 1)
4. Frame sync active (for continuous clock case)
5. Bit clock begins (for gated clock case)
With the above conditions in normal mode with a continuous clock, each time the frame sync signal is
generated (or detected), a data word is clocked in. With the above conditions and a gated clock, each time
the clock begins, a data word is clocked in.
If receive FIFO 0 is not enabled, the received data word is transferred from the receive shift register
(RXSR) to the receive data register 0 (SSI_RX0), and the RDR0 flag is set. Receive interrupt 0 occurs if
the RIE and SSI_IER[RDR0] bits are set.
If receive FIFO 0 is enabled, the received data word is transferred to the receive FIFO 0. The RFF0 flag is
set if the receive data register (SSI_RX0) is full and receive FIFO 0 reaches the selected threshold. Receive
interrupt 0 occurs if RIE and SSI_IER[RFF0] bits are set.
The core has to read the data from the SSI_RX0 register before a new data word is transferred from the
RXSR; otherwise, receive overrun error 0 (ROE0) bit is set. If receive FIFO 0 is enabled, the ROE0 bit is
set when the receive FIFO 0 data level reaches the selected threshold and a new data word is ready to
transfer to the receive FIFO 0.
Figure 27-27 shows transmitter and receiver timing for an 8-bit word with two words per time slot in
normal mode and continuous clock with a late word length frame sync. The Tx data register is loaded with
the data to be transmitted. On arrival of the frame sync, this data is transferred to the transmit shift register
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