Freescale Semiconductor SC140 DSP Core Manuals

Manuals and User Guides for Freescale Semiconductor SC140 DSP Core. We have 1 Freescale Semiconductor SC140 DSP Core manual available for free PDF download: Reference Manual

Freescale Semiconductor SC140 DSP Core Reference Manual

Freescale Semiconductor SC140 DSP Core Reference Manual (760 pages)

digital signal processor (DSP) core

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 8 MB

Table of Contents

Table of Contents
3
List of Figures
13
List of Tables
15
Audience
23
Organization
23
About this Book

23
- Abbreviations
  24
- Revision History
  26
Chapter 1 Introduction

27
Chapter 2 Core Architecture

33
Chapter 3 Control Registers

101
- Core Control Registers
  101
- Status Register (SR)
  101
  - Status Register Description
    102
- Exception and Mode Register (EMR)
  107
  - EMR Description
    108
- Clearing EMR Bits
  110
- PLL and Clock Registers
  110
Chapter 4 Emulation and Debug (Eonce)

111
- Debugging System
  111
- Overview of the Combined JTAG and Eonce Interface
  112
- Cascading Multiple SC140 Eonce Modules in a Soc
  112
  - JTAG Interface Signal Descriptions
    112
- JTAG Scan Paths
  113
  - JTAG and Eonce Multi-Core Interconnection
    113
  - TAP Controller State Machine
    115
  - JTAG Scan Paths
    115
- Activating the Eonce through the JTAG Port
  116
- Enabling the Eonce Module
  116
- DEBUG_REQUEST and ENABLE_EONCE Commands
  117
- Reading/Writing Eonce Registers through JTAG
  117
- Main Capabilities of the Eonce Module
  120
- Eonce Signals
  120
  - Typical Debugging System
    120
- Eonce Dedicated Instructions
  121
- Debug State
  121
- Debug Exception
  122
- Executing an Instruction While in Debug State
  122
- Software Downloading
  122
  - Software Downloading
    123
- Eonce Events
  124
- Eonce Actions
  125
- Event and Action Summary
  125
- Eonce Enabling and Power Considerations
  126
- Eonce Module Internal Architecture
  126
- Eonce Controller
  126
  - Eonce Controller Block Diagram
    127
  - Eonce Controller Register Set
    127
- Event Counter
  128
  - Event Counter Block Diagram
    129
  - Event Counter Register Set
    129
- Event Detection Unit (EDU)
  130
  - Event Detection Unit Block Diagram
    131
- Address Event Detection Channel (EDCA)
  132
  - EDCA Block Diagram
    132
- Data Event Detection Channel (EDCD)
  134
  - EDCD Block Diagram
    134
- Optional External Event Detection Address Channels
  135
- Event Selector (ES)
  135
- Trace Unit
  136
  - Event Selector Block Diagram
    136
- Change of Flow and Interrupt Tracing
  138
  - Trace Unit Block Diagram
    138
- Writing to the Trace Buffer
  139
- Reading the Trace Buffer (TB_BUFF)
  139
- Trace Unit Programming Model
  139
- Eonce Register Addressing
  140
  - Trace Buffer Register Set
    140
  - Eonce Register Addressing Offsets
    141
- Reading or Writing Eonce Registers Using Core Software
  143
- Real-Time JTAG Access
  143
- Real-Time Data Transfer
  144
- General Eonce Register Issues
  144
- Eonce Controller Registers
  146
- Eonce Command Register (ECR)
  146
- Eonce Status Register (ESR)
  147
  - Eonce Status Register (ESR)
    148
- Eonce Monitor and Control Register (EMCR)
  151
- Eonce Receive Register (ERCV)
  153
- Eonce Transmit Register (ETRSMT)
  153
- EE Signals
  154
- EE Signals as Outputs
  154
- EE Signals as Inputs
  155
- EE Signals Control Register (EE_CTRL)
  155
- Core Command Register (CORE_CMD)
  158
  - Injected Instruction Format
    158
  - Length Control Bits
    158
- PC of the Exception Execution Set (PC_EXCP)
  159
- PC of the Next Execution Set (PC_NEXT)
  159
- PC of Last Execution Set (PC_LAST)
  159
- PC Breakpoint Detection Register (PC_DETECT)
  159
- Event Counter Registers
  160
- Event Counter Control Register (ECNT_CTRL)
  160
- Event Counter Value Register (ECNT_VAL)
  162
- Extension Counter Value Register (ECNT_EXT)
  163
- EC Signals
  163
- Event Detection Unit (EDU) Channels and Registers
  164
- Address Event Detection Channel (EDCA)
  164
- EDCA Control Registers (Edcai_Ctrl)
  164
  - EDCA Mask Register (Edcai_Mask)
    167
- Data Event Detection Channel (EDCD)
  168
- EDCD Control Register (EDCD_CTRL)
  168
- EDCD Reference Value Register (EDCD_REF)
  171
- EDCD Mask Register (EDCD_MASK)
  171
- Event Selector (ES) Registers
  171
- Event Selector Control Register (ESEL_CTRL)
  171
- Event Selector Mask Debug State Register (ESEL_DM)
  173
- Event Selector Mask Debug Exception
  174
  - Register (ESEL_DI)
    174
  - Event Selector Mask Enable Trace Register (ESEL_ETB)
    174
- Event Selector Mask Disable Trace Register (ESEL_DTB)
  175
- Trace Unit Registers
  175
- Trace Buffer Control Register (TB_CTRL)
  175
- Trace Buffer Read Pointer Register (TB_RD)
  179
- Trace Buffer Write Pointer Register (TB_WR)
  179
- Trace Buffer Register (TB_BUFF)
  179
Chapter 5

181
- Pipeline
  181
- Instruction Pipeline Stages
  182
  - Pipeline Example
    183
  - Pipeline Stages Overview
    183
- Instruction Pre-Fetch and Fetch
  184
- Instruction Dispatch
  184
- Address Generation
  184
- Execution
  185
- Instruction Grouping
  185
- Grouping Types
  186
  - Instruction Grouping Methods
    186
- Serial Grouping
  187
- Prefix Grouping
  187
- Prefix Types
  188
- Two-Word Prefix
  188
- One-Word Low Register Prefix
  189
- Conditional Execution
  189
- Prefix Selection Algorithm
  190
  - Low Register Prefix Selection Algorithm
    191
- Instruction Reordering Within an Execution Set
  192
- Instruction Timing
  194
- Sequential Instruction Timing
  195
- DALU Instruction Timing
  196
- Move Instruction Timing
  196
- Bit Mask Instruction Timing
  196
- Change-Of-Flow Instruction Timing
  197
  - Non-Loop Change-Of-Flow Instructions
    197
- Direct, PC-Relative, and Conditional COF
  198
  - Loop Change-Of-Flow Instructions
    198
- Delayed COF
  199
- COF Execution Cycles
  199
  - Number of Cycles Needed by Change-Of-Flow Instructions
    200
- Memory Access Timing
  201
- Memory Access Examples
  202
- Implicit Push/Pop Memory Timing
  204
- Memory Stall Conditions
  204
- Hardware Loops
  205
- Loop Programming Model
  205
- Loop Start Address Registers (San)
  205
  - Hardware Loop Programming Model
    205
- Loop Counter Registers (Lcn)
  206
- Status Register (SR) Loop Flag Bits
  206
- Loop Notation and Encoding
  206
- Loop Initiation and Execution
  207
  - LPMARKA and LPMARKB Bits in Short and Long Loops
    207
- Loop Nesting
  208
- Loop Iteration and Termination
  208
- Loop Control Instructions
  209
- Loop Timing
  212
- Stack Support
  212
- SC140 Single Stack Memory Use
  212
  - SC140 Memory Use with a Single Stack Pointer
    212
- SC140 Dual Stack Memory Use
  213
  - SC140 Memory Use with Dual Stack Pointers
    213
- Stack Support Instructions
  214
- Shadow Stack Pointer Registers
  215
- Fast Return from Subroutines
  216
- Working Modes
  217
- Normal Working Mode
  217
- Exception Working Mode
  217
- Typical Working Mode Usage Scenarios
  218
- Dual-Stack RTOS
  218
  - Working Mode Transitions - Unprotected Dual-Stack RTOS
    218
- Single-Stack RTOS
  219
- Working Mode Transitions
  219
- From Exception to Normal Mode
  219
- From Normal to Exception Mode
  219
  - Working Mode Transitions - Unprotected Single-Stack RTOS
    219
- Processing States
  221
- Processing State Change Instructions
  221
- Processing State Transitions
  222
  - Core State Diagram
    222
- Execution State
  223
- Reset Processing State
  223
  - Processing State Transitions
    223
- Debug State
  224
- Wait Processing State
  224
- Stop Processing State
  225
  - Exit Wait Processing State Due to an Interrupt or NMI
    225
- Exception Processing
  226
  - Core-PIC Interface
    227
- Interrupt Vector Address
  228
- Vector Base Address Register
  228
- Programming Exception Routine Addresses
  228
- Return from Exception Instructions
  229
  - Exception Vector Address Table
    229
- Maskable Interrupts
  230
- Interrupt Priority Level
  230
- Controlling All Interrupt Sources
  230
- Non-Maskable Interrupts (NMI)
  230
- Internal Exceptions
  230
- Illegal Exception
  231
- DALU Overflow
  232
- TRAP Exception
  232
- Debug Exception
  232
- Exception Interface to the Pipeline
  232
- Exception Routine Fetch
  232
- Exception Mode Execution
  233
- Exception Timing
  233
  - Exception Pipeline
    233
  - Flowchart for Exception Timing
    235
  - Pipeline Example
    236
Chapter 6 Instruction Set Accelerator Plug-In

237
- Introduction
  237
- ISAP - SC140 Schematic Connection
  238
- Single ISAP
  238
  - Core to Single ISAP Connection Schematic
    238
- Multiple ISAP
  239
  - Core to Multiple ISAP Connection Schematic
    239
- ISAP Instructions and Instruction Encoding
  240
- ISAP Memory Access
  240
  - ISAP Encoding Fields
    240
- ISAP-Core Register Transfers
  241
- Immediate Data Transfer to ISAP Registers
  242
- Core Assembly Syntax with an ISAP
  243
- Identification of ISAP Instructions
  243
- Working with One ISAP
  243
- Working with Multiple Isaps
  244
- An Example of the Definition Flexibility of an ISAP
  245
- Conditional Execution
  246
Programming Rules

247
Chapter 7

251
- VLES Sequencing Semantics
  251
- VLES Grouping Semantics
  251
- SC140 Pipeline Exposure
  253
- Programming Rule Notation
  253
- Grouping Rules
  253
- Prefix Instructions
  253
- Conditional Subgroups
  253
- Assembler Reordering
  253
- Sequencing Rules
  254
- Cycle Counts
  254
- Conditional Execution
  254
- Simulator Execution Counts
  254
- Register Read/Write
  254
- Register Names
  254
- B Register Aliasing
  255
- Status Bit Updates
  255
- Instruction Words
  255
- MOVE-Like Instructions
  255
- Address/Data Operands
  255
- AGU Arithmetic Instructions
  256
- Change-Of-Flow Destinations
  256
- COF Instructions
  256
- Delayed COF Instructions
  256
  - Delay Slot
    256
- Hardware Loops
  257
- Enabled Loop
  257
- Enveloping Loop
  257
- Static Programming Rules
  257
- Hardware Loop Detection
  257
- General Grouping Rules
  258
- Prefix Grouping Rules
  261
  - Prefix Instructions
    262
- AGU Rules
  266
- Delayed COF Rules
  269
- Status Bit Rules
  272
- Loop Nesting Rules
  278
- Loop la Rules
  281
- Loop Sequencing Rules
  283
- Loop COF Rules
  286
- General Looping Rules
  290
- Dynamic Programming Rules
  291
- AGU Dynamic Rules
  291
- Memory Access Rules
  292
- RAS Rules
  293
- Loop Rules
  293
- Rule Detection Across COF Boundaries
  294
- Cycle-Based COF Rules
  294
- VLES-Based COF Rules
  295
- Rule Detection Across Exception Boundaries
  296
- Programming Guidelines
  298
- Rules Not Detected Across COF Boundaries
  299
- Good Programming Practices
  299
- Source Code Practices
  299
- Binary Code Practices
  300
- Software Development Practices
  301
- LPMARK Rules
  301
- LPMARK Instruction Type
  301
- Static Programming Rules
  302
- General Grouping Rules
  302
- Prefix Grouping Rules
  302
- Dynamic Programming Rules
  302
- LPMARK Notation
  302
- Loop Nesting Rules
  303
- Loop la Rules
  303
- Loop Sequencing Rules
  305
- Loop COF Rules
  306
- General Looping Rules
  309
- Rule Detection Across Exception Boundaries
  309
- LPMARK Programming Guidelines
  309
- NOP Definition
  310
- Grouping Examples
  311
Appendix A SC140 DSP Core Instruction Set

315
- Introduction
  315
- A.1 Introduction
  315
- Conventions
  316
  - A.1.1 Conventions
    316
  - Instruction Conventions
    316
  - Operations Syntax
    317
  - Register Abbreviations
    317
- Brackets as ISAP Indicators
  318
- Brackets as Address Indicators
  318
  - Assembler Syntax
    318
- Addressing Mode Notation
  319
  - Addressing Mode Notation for the EA Operand
    319
- Data Representation in Memory for the Examples
  320
- Encoding Notation
  320
- A.1.4 Encoding Notation
  320
- Prefix Word Encoding
  321
- One-Word Low Register Prefix
  322
- Two-Word Prefix
  323
- Instruction Types
  326
- A.1.6 Instruction Types
  326
- Instruction Sub-Types
  326
- Instructions
  326
  - DALU Logical Instructions (BFU
    328
  - AGU Move Instructions
    330
  - AGU Bit-Mask Instructions (BMU
    331
- A.2 Instructions
  333
- Instruction Definition Layout
  333
  - And
    354
  - Ln Bit Calculation
    362
  - Asl2A
    364
  - Asla
    365
  - Asll
    366
- Aslw
  369
  - Asr
    371
  - Asra
    373
- Asrr
  374
  - Bit Mask
    383
  - Bmchg
    383
  - Bmchg.w
    386
  - Bmclr
    389
  - Bmclr.w
    392
  - Bmset
    394
  - Bmset.w
    396
  - Bmtset
    398
  - Bmtset.w
    400
  - Bmtstc
    403
  - Bmtstc.w
    405
  - Bmtsts
    408
  - Bmtsts.w
    410
  - Bra
    413
  - Brad
    415
  - Break
    417
  - Bsr
    419
  - Bsrd
    421
  - Btd
    425
  - C (Carry Bit)
    492
  - Combinations of Lpmarkx Use
    536
  - B.1 Using the Starcore Registry
    747
  - SCID Assignments
    748
  - Conditional
    750

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