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Fast Ethernet Controllers (FEC0 and FEC1)
The MIB_DIS bit is reset to 1. See
Address: 0xFC03_0064 (MIBC0)
0xFC03_4064 (MIBC1)
31
30
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
MIB_
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MIB_
IDLE
DIS
W
Reset
1
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31
A read/write control bit. If set, the MIB logic halts and not update any MIB counters.
MIB_DIS
30
A read-only status bit. If set the MIB block is not currently updating any MIB counters.
MIB_IDLE
29–0
Reserved.
26.4.10 Receive Control Registers (RCR0 & RCR1)
RCRn controls the operational mode of the receive block and must be written only when
ECRn[ETHER_EN] is cleared (initialization time).
Address: 0xFC03_0084 (RCR0)
0xFC03_4084 (RCR1)
31
30
29
R
0
0
0
W
Reset
0
0
0
15
14
13
R
0
0
0
W
Reset
0
0
0
Field
31–27
Reserved, must be cleared.
26–16
Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the
MAX_FL
end of the frame. Transmit frames longer than MAX_FL causes the BABT interrupt to occur. Receive frames longer
than MAX_FL causes the BABR interrupt to occur and sets the LG bit in the end of frame receive buffer descriptor.
The recommended default value to be programmed is 1518 or 1522 if VLAN tags are supported.
26-19
Table 26-4
for the locations of the MIB counters.
Figure 26-9. MIB Control Register (MIBCn)
Table 26-13. MIBCn Field Descriptions
28
27
26
25
0
0
0
0
1
0
12
11
10
9
RMII_
0
RMII_
RMII_
RMII_
MODE
ECHO
LOOP
10T
0
0
0
0
Figure 26-10. Receive Control Register (RCRn)
Table 26-14. RCRn Field Descriptions
Description
24
23
22
21
MAX_FL
1
1
1
1
8
7
6
5
0
0
BC_
FCE
REJ
0
0
0
0
Description
Access: User read/write
8
7
6
5
4
3
2
1
0
Access: User read/write
20
19
18
17
0
1
1
1
4
3
2
1
MII_
PROM
DRT LOOP
MODE
0
0
0
0
Freescale Semiconductor
16
0
0
1
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