Caching Modes - Freescale Semiconductor MCF54455 Reference Manual

Cache
Valid cache entries that match during cache-inhibited address accesses are neither pushed nor invalidated.
Such a scenario suggests that the associated cache mode for this address space was changed. To avoid this,
use the CPUSHL instruction to push or invalidate the cache entry or set CACR[DCINVA] to invalidate the
data cache before switching cache modes.
6.4.1

Caching Modes

For every memory reference the processor or debug module generates, a set of effective attributes is
determined based on the address and ACRs. Caching modes determine how the cache handles an access.
A data access can be cacheable in write-through or copyback mode; it can be cache-inhibited in precise or
imprecise modes. For normal accesses, the ACRn[CM] bit corresponding to the address of the access
specifies the caching modes. If an address does not match an ACR, the default caching mode is defined by
CACR[DDCM,IDCM]. The specific algorithm is as follows:
if (address == ACR0-address including mask)
effective attributes = ACR0 attributes
else if (address == ACR1-address including mask)
effective attributes = ACR1 attributes
else effective attributes = CACR default attributes
Addresses matching an ACR can also be write-protected using ACR[W]. Addresses that do not match
either ACR can be write-protected using CACR[DW].
Reset disables the cache and clears all CACR bits. As shown in
invalidate cache entries; the software invalidates them.
The ACRs allow the defaults selected in the CACR to be overridden. In addition, some instructions (for
example, CPUSHL) and processor core operations perform accesses that have an implicit caching mode
associated with them. The following sections discuss the different caching accesses and their associated
cache modes.
6.4.1.1 Cacheable Accesses
If ACRn[CM] or the default field of the CACR indicates write-through or copyback, the access is
cacheable. If matching data is found, a read access to a write-through or copyback region is read from the
cache. Otherwise, the data is read from memory, and the cache is updated. When a line is read from
memory for either a write-through or copyback read miss, the longword within the line that contains the
core-requested data is loaded first, and the requested data is given immediately to the processor, without
waiting for the three remaining longwords to reach the cache.
The following sections describe write-through and copyback modes in detail. Some of this information
applies to data caches only.
6.4.1.1.1 Write-Through Mode (Data Cache Only)
Write accesses to regions specified as write-through are always passed on to the external bus; although the
cycle can be buffered, depending on the state of CACR[DESB]. Writes in write-through mode are handled
with a no-write-allocate policy—that is, writes that miss in the cache are written to the external bus but do
not cause the corresponding line in memory to load into the cache. Write accesses that hit always write
6-12
Figure 6-3, reset does not automatically
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