Freescale Semiconductor MCF54455 Reference Manual page 849

Debug Module
system running on the processor core. Software guarantees that accesses to these resources are serialized
and logically consistent. Hardware provides a locking mechanism in CSR to allow external development
system to disable any attempted writes by the processor to the breakpoint registers (setting CSR[IPW]).
BDM commands must not be issued if the ColdFire processor is using the WDEBUG instruction to access
debug module registers, or the resulting behavior is undefined. The DSCLK must be quiescent during
operation of the WDEBUG command.
These registers, shown in
implemented bits. These registers are also accessed through the BDM port by the commands,
and , described in
RDMREG
DRc, that specifies the register, as shown in
DRc[4–0]
0x00 Configuration/status register (CSR)
0x05 BDM address attribute register (BAAR)
0x06 Address attribute trigger register (AATR)
0x07 Trigger definition register (TDR)
0x08 PC breakpoint register 0 (PBR0)
0x09 PC breakpoint mask register (PBMR)
0x0A PC breakpoint ASID control (PBAC)
0x0C Address breakpoint high register (ABHR)
0x0D Address breakpoint low register (ABLR)
0x0E Data breakpoint register (DBR)
0x0F Data breakpoint mask register (DBMR)
0x14 PC breakpoint ASID register (PBASID)
0x16 Address attribute trigger register 1 (AATR1)
0x17 Extended trigger definition register (XTDR)
0x18 PC breakpoint register 1 (PBR1)
0x1A PC breakpoint register 2 (PBR2)
0x1B PC breakpoint register 3 (PBR3)
0x1C Address high breakpoint register 1 (ABHR1)
0x1D Address low breakpoint register 1 (ABLR1)
0x1E Data breakpoint register 1 (DBR1)
0x1F Data breakpoint mask register 1 (DBMR1)
1
Each debug register is accessed as a 32-bit register; reserved fields are not used (don't care).
34-7
Table 34-5, are treated as 32-bit quantities, regardless of the number of
Section 34.4.1.5, "BDM Command Set".
Table
Table 34-5. Debug Module Memory Map
Register Name
These commands contain a 5-bit field,
34-5.
Width
Access
(bits)
32 R/W
See Note
1
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
32 W
WDMREG
Section/
Reset Value
Page
0x00B0_0000 34.3.2/34-9
0x05 34.3.3/34-11
0x0000_0005 34.3.4/34-12
0x0000_0000 34.3.5/34-14
Undefined 34.3.6/34-17
Undefined 34.3.6/34-17
Undefined 34.3.7/34-18
Undefined 34.3.8/34-19
Undefined 34.3.8/34-19
Undefined 34.3.9/34-20
Undefined 34.3.9/34-20
Undefined 34.3.10/34-21
0x0005 34.3.4/34-12
0x0000_0000 34.3.11/34-22
See Section 34.3.6/34-17
See Section 34.3.6/34-17
See Section 34.3.6/34-17
Undefined 34.3.8/34-19
Undefined 34.3.8/34-19
Undefined 34.3.9/34-20
Undefined 34.3.9/34-20
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