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Freescale Semiconductor MC68HC08KH12 Datasheet

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MC68HC08KH12
Data Sheet
M68HC08
Microcontrollers
Rev. 1.1
MC68HC08KH12/H
July 15, 2005
freescale.com

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Summary of Contents for Freescale Semiconductor MC68HC08KH12

  • Page 1 MC68HC08KH12 Data Sheet M68HC08 Microcontrollers Rev. 1.1 MC68HC08KH12/H July 15, 2005 freescale.com...

  • Page 3: Table Of Contents

    Section 14. External Interrupt (IRQ) ... 213 Section 15. Keyboard Interrupt Module (KBI) ... 219 Section 16. Break Module (BREAK) ... 241 Section 17. Preliminary Electrical Specifications ... 247 Section 18. Mechanical Specifications ... 259 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor List of Sections Advance Information...
  • Page 4 Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 5 Rev. 1.1 — Freescale Semiconductor General Description Contents ......... .23 Introduction .
  • Page 6 Condition Code Register (CCR) ..... 57 Arithmetic/Logic Unit (ALU) ......59 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 7 Rev. 1.1 — Freescale Semiconductor Section 7. System Integration Module (SIM) Contents ......... .61 Introduction .
  • Page 8 ) ..... . 98 ) ..... . 98 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 9 — Freescale Semiconductor Interrupts.........107 Special Modes .
  • Page 10 Interrupts.........171 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 11 — Freescale Semiconductor Wait Mode........171 TIM During Break Interrupts .
  • Page 12 Features ......... 213 Functional Description ......214 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 13 Rev. 1.1 — Freescale Semiconductor IRQ1/V Pin ........215 IRQ Module During Break Interrupts .
  • Page 14 Oscillator Characteristics ......251 USB DC Electrical Characteristics ..... 252 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 15 Rev. 1.1 — Freescale Semiconductor CGM Component Specifications ....257 CGM Electrical Specifications ..... . 257 Acquisition/Lock Time Specifications .
  • Page 16 Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 17: List Of Figures

    Rev. 1.1 — Freescale Semiconductor Title MCU Block Diagram ....... . . 27 64-Pin QFP Assignments (Top View) .
  • Page 18 (UE0D0-UE0D7) ....... . 147 Page MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 19 Rev. 1.1 — Freescale Semiconductor Title (UE0D0-UE0D7) ....... . 148...
  • Page 20 16-3 Break Address Registers (BRKH and BRKL) ... . . 246 18-1 64-Pin Quad-Flat-Pack (Case 840C-04)....260 Advance Information Title MC68HC(7)08KH12 — Freescale Semiconductor Page Rev. 1.1...

  • Page 21: List Of Tables

    11-1 TIM I/O Register Summary ...164 11-2 Prescaler Selection... 175 11-3 Mode, Edge, and Level Selection ... 180 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Title Vector Addresses ...43 Signal Name Conventions ... 65 PIN Bit Set Timing ... 67 Interrupt Sources ... 76 SIM Registers ...
  • Page 22 12-7 Port F Pin Functions ... 204 13-1 COP I/O Port Register Summary... 208 14-1 IRQ I/O Port Register Summary ... 215 15-1 KBI I/O Register Summary ...221 16-1 Break I/O Register Summary... 243 Advance Information Title MC68HC(7)08KH12 — Freescale Semiconductor Page Rev. 1.1...

  • Page 23: Contents

    Rev. 1.1 — Freescale Semiconductor Section 1. General Description Introduction ........24 Features .

  • Page 24: Introduction

    • 6 MHz Internal Bus Operation • Low-Power Design (Fully Static with Stop and Wait Modes) • 12 KBytes of User ROM (MC68HC08KH12) or One-Time Programmable (OTP) ROM (MC68HC708KH12) • On-Chip Programming Firmware for Use with Host Personal Computer •...
  • Page 25 1. Embedded device supports only bulk and interrupt transfers, and does not support isochronous transfers. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Full Universal Serial Bus Specification 1.1 Composite HUB with Embedded Functions: – 1 × 12MHz Upstream Port – 4 × 12MHz/1.5MHz Downstream Ports –...

  • Page 26: Mcu Block Diagram

    Fast 16/8 Divide Instruction • Binary-Coded Decimal (BCD) Instructions • Optimization for Controller Applications • Third Party C Language Support 1.4 MCU Block Diagram Figure 1-1 Advance Information shows the structure of the MC68HC(7)08KH12. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 27: Mcu Block Diagram

    PTC4–PTC0 PTD7/KBD7– PORT C PTD0/KBD0 DDRC PTE4 PTE3/KBE3– PTE0/KBE0 PTF7/KBF7– PTF0/KBF0 CPU REGISTERS DPLUS4 DS Port 4 DMINUS4 DPLUS3 DS Port 3 DMINUS3 CONDITION CODE REGISTER DPLUS2 DS Port 2 DMINUS2 DPLUS1 DS Port 1 DMINUS1 DPLUS0 US Port DMINUS0 Embedded USB Function PORTS ARE SOFTWARE CONFIGURABLE WITH PULLUP DEVICE IF INPUT PORT SOFTWARE CONFIGURABLE LED DIRECT DRIVE 3mA SOURCE /10mA SINK or STANDARD DRIVE...

  • Page 28: Pin Assignments

    DMINUS3 DPLUS4 DMINUS4 Figure 1-2. 64-Pin QFP Assignments (Top View) Advance Information Shows the 64-pin QFP assignments. 68HC(7)08KH12 PTA3 PTA2 PTA1 PTA0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 PTD7/KBD7 PTD6/KBD6 PTD5/KBD5 PTD4/KBD4 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 29: Power Supply Pins

    MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor and V are the analog power supply and ground pins used by and V are the power supply and ground pins used by the and V are the power supply and ground pins to the I/O pads.

  • Page 30: Oscillator Pins (Osc1 And Osc2)

    ((See Section 7. System Integration Module is an asynchronous external interrupt pin. IRQ1/V (See Section 14. External Interrupt (See Section 9. Universal Serial Bus (USB).) (USB).) (CGM).) is also pin contain an (IRQ).) (See Section 9. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 31: Port A Input/Output (I/O) Pins (Pta7-Pta0)

    PTE3-PTE0 has built-in optical coupling interface for optical mouse application. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Ports.) Each pin contains a software configurable pull- Ports.) Each pin contains a software configurable pull- Ports.) Port C pins are software configurable to be LED (See Section 12. I/O Ports.) Any or all of the port D pins can be...

  • Page 32: Port F I/O Pins (Ptf7/Kbf7-Ptf0/Kbf0)

    PTF7/KBF7–PTF0/KBF0 are general-purpose bidirectional I/O port pins. (See Section 12. I/O programmed to serve as external interrupt pins. Keyboard Interrupt Module Advance Information Ports.) Any or all of the port F pins can be (See Section 15. (KBI).) MC68HC(7)08KH12 Freescale Semiconductor Rev. 1.1 —...

  • Page 33: Section 2. Memory Map

    Rev. 1.1 — Freescale Semiconductor Section 2. Memory Map Introduction ........33 I/O Section .

  • Page 34: Memory Map

    ↓ MONITOR ROM (240 BYTES) $FEFF $FF00 $FF00 to $FF8C ↓ UNIMPLEMENTED (141 BYTES) $FF8D RESERVED ↓ $FF8E to $FFE5 $FFE5 UNIMPLEMENTED (88 BYTES) $FFE6 ↓ VECTORS (26 BYTES) $FFFF Figure 2-1. Memory Map MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 35: I/O Section

    • • • • MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor $FE00 (Break Status Register, BSR) $FE01 (Reset Status Register, RSR) $FE02 (Reserved) $FE03 (Break Flag Control Register, BFCR) $FE04 (Interrupt Status Register 1, INT1) $FE05 (Interrupt Status Register 2, INT2)

  • Page 36: Control, Status, And Data Registers

    PTE3 PTE2 PTE1 PTE0 PTF3 PTF2 PTF1 PTF0 DDRE3 DDRE2 DDRE1 DDRE0 DDRF3 DDRF2 DDRF1 DDRF0 KEYDF IMASKD MODED ACKD KBDIE3 KBDIE2 KBDIE1 KBDIE0 KEYEF IMASKE MODEE ACKE KBEIE3 KBEIE2 KBEIE1 KBEIE0 = Reserved MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 37 IRQ Status and Control Register $001E (ISCR) Configuration Register $001F (CONFIG) † One-time writable register Figure 2-2. Control, Status, and Data Registers (Continued) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Bit 7 TOIE TSTOP (TSC) Bit 15 Bit 7 Bit 15 Bit 7 CH0F CH0IE...
  • Page 38 W: DE1T47 DE1T46 DE1T45 DE1T44 DE1T43 DE1T42 DE1T41 DE1T40 W: DE1T57 DE1T56 DE1T55 DE1T54 DE1T53 DE1T52 DE1T51 DE1T50 W: DE1T67 DE1T66 DE1T65 DE1T64 DE1T63 DE1T62 DE1T61 DE1T60 W: DE1T77 DE1T76 DE1T75 DE1T74 DE1T73 DE1T72 DE1T71 DE1T70 = Unimplemented Bit 0 = Reserved MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 39 Figure 2-2. Control, Status, and Data Registers (Continued) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Bit 7 R: HE0R07 HE0R06 HE0R05 HE0R04 HE0R03 HE0R02 HE0R01 HE0R00 W: HE0T07 HE0T06 HE0T05 HE0T04 HE0T03 HE0T02 HE0T01 HE0T00 R: HE0R17 HE0R16 HE0R15 HE0R14 HE0R13 HE0R12 HE0R11 HE0R10...
  • Page 40 KBFIE1 KBFIE0 PFPE3 PFPE2 PFPE1 PFPE0 DSTALL1 ENABLE2 ENABLE1 DSTALL2 DADD3 DADD2 DADD1 DADD0 TXD0IE RXD0IE TXD0FR RXD0FR TXD1IE TXD1FR TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 = Reserved MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 41 USB HUB Status Register (HSR) USB HUB Root Port Control $005E Register (HRPCR) $005F Unimplemented Figure 2-2. Control, Status, and Data Registers (Continued) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Bit 7 PEN1 LOWSP1 RST1 RESUM1 SUSP1 PEN2 LOWSP2 RST2 RESUM2 SUSP2...
  • Page 42 Bit 7 ILOP BCFE IF11 Bit 15 Bit 7 BRKE BRKA Low byte of reset vector Writing clears COP counter (any value) = Unimplemented Bit 0 SBSW ILAD IF10 Bit 8 Bit 0 = Reserved MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 43: Monitor Rom

    The 240 bytes at addresses $FE10–$FEFF are reserved ROM addresses that contain the instructions for the monitor functions. Section 10. Monitor ROM MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor is a list of vector locations. Table 2-1. Vector Addresses Address $FFE6 PLL Vector (High)
  • Page 44 Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 45: Section 3. Random-Access Memory (Ram)

    — Freescale Semiconductor Introduction ........45 Functional Description .
  • Page 46 The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 47: Section 4. Read-Only Memory (Rom)

    4.1 Contents 4.2 Introduction This section describes the 11,776 bytes of read-only memory (ROM) and 26 bytes of user vectors, available on the MC68HC08KH12 device (ROM part). On the MC68HC708KH12 (OTP part), the ROM is replaced with 11,776 bytes One-Time Programmable (OTP) ROM. Programming tools are available from Freescale.
  • Page 48 Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 49: Section 5. Configuration Register (Config)

    MCU it is recommended that this register be written immediately after reset. The configuration register is located at $001F. The configuration register may be read at anytime. This configuration register exists on both the MC68HC708KH12 (OTP part) and MC68HC08KH12 (ROM part). MC68HC(7)08KH12 Rev. 1.1 —...

  • Page 50: Configuration Register (Config)

    0 = COP module enabled Advance Information $001F Bit 7 = Unimplemented Figure 5-1. Configuration Register (CONFIG) –2 )×CGMXCLK –2 )×CGMXCLK See Section 13. Computer (COP). Figure 5-1. Bit 0 SSREC COPRS STOP COPD MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 51: Section 6. Central Processor Unit (Cpu)

    Rev. 1.1 — Freescale Semiconductor Section 6. Central Processor Unit (CPU) Introduction ........51 Features .

  • Page 52: Features

    Extension of Addressing Range Beyond 64 Kbytes • Low-Power Stop and Wait Modes 6.4 CPU Registers Figure 6-1 the memory map. Advance Information shows the five CPU registers. CPU registers are not part of MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 53: Accumulator (A)

    Read: Write: Reset: MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor V 1 1 H I N Z C Figure 6-1. CPU Registers Bit 7 Unaffected by reset Figure 6-2. Accumulator (A) ACCUMULATOR (A) INDEX REGISTER (H:X)

  • Page 54: Index Register (H:x)

    Read: Write: Reset: The index register can serve also as a temporary data storage location. Advance Information X = Indeterminate Figure 6-3. Index Register (H:X) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 55: Stack Pointer (Sp)

    RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct address (page zero) space. For correct operation, the stack pointer must point only to RAM locations. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Figure 6-4. Stack Pointer (SP) Advance Information...

  • Page 56: Program Counter (Pc)

    $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Read: Write: Reset: Advance Information Loaded with vector from $FFFE and $FFFF Figure 6-5. Program Counter (PC) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 57: Condition Code Register (Ccr)

    The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Bit 7 X = Indeterminate Figure 6-6. Condition Code Register (CCR) 1 = Overflow 0 = No overflow...
  • Page 58 Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 59: Arithmetic/Logic Unit (Alu)

    Refer to the CPU08 Reference Manual (Freescale document number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about CPU architecture. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = Carry out of bit 7 0 = No carry out of bit 7 Advance Information...
  • Page 60 Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 61: Section 7. System Integration Module (Sim)

    — Freescale Semiconductor Introduction ........62 SIM Bus Clock Control and Generation .

  • Page 62: Introduction

    Break Flag Control Register (BFCR)....85 Figure 7-1. Figure 7-2 is a summary of the SIM I/O registers. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 63: Sim Block Diagram

    RESET PIN LOGIC SIM RESET STATUS REGISTER MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor STOP/WAIT CONTROL COUNTER ÷2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET RESET PIN CONTROL CONTROL RESET INTERRUPT CONTROL AND PRIORITY DECODE Figure 7-1. SIM Block Diagram...

  • Page 64: Sim I/O Register Summary

    Figure 7-2. SIM I/O Register Summary Advance Information Bit 7 Read: Write: Read: ILOP Write: Read: BCFE Write: Read: Write: Read: IF11 Write: Read: Write: = Unimplemented Bit 0 SBSW ILAD IF10 = Reserved for factory test MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 65: Sim Bus Clock Control And Generation

    In user mode, the internal bus frequency is the oscillator frequency (CGMXCLK) divided by four. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor shows the internal signal names used in this section. Table 7-1. Signal Name Conventions Signal Name CGMXCLK Buffered OSC1 from the oscillator The CGMXCLK frequency divided by two.

  • Page 66: Clock Start-Up From Por

    (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. Advance Information (See 7.7.2 Stop Mode.) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 67: External Pin Reset

    SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor (See 7.8 SIM Table 7-2 for details. Table 7-2. PIN Bit Set Timing Reset Type...

  • Page 68: Power-On Reset

    Advance Information RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 7-5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET Figure 7-6. Sources of Internal Reset MC68HC(7)08KH12 VECTOR HIGH Rev. 1.1 — Freescale Semiconductor...

  • Page 69: Computer Operating Properly (Cop) Reset

    RST or the IRQ1/V from becoming disabled as a result of external noise. During a break state, V MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 4096 CYCLES CYCLES Figure 7-7. POR Recovery – 2 CGMXCLK cycles, drives the COP counter. The COP while the MCU is in monitor mode.

  • Page 70: Illegal Opcode Reset

    Reset can wake a device from the suspended mode. A device may take up to 10 ms to wake up from the suspended state. Advance Information µ s may treat that signal as µ MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 71: Sim Counter

    External reset has no effect on the SIM counter. for details.) The SIM counter is free-running after all reset states. 7.4.2 Active Resets from Internal Sources internal reset recovery sequences.) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor (See 7.7.2 Stop Mode (See for counter control and Advance Information...

  • Page 72: Exception Control

    Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). Advance Information Figure 7-8 flow charts the handling of MC68HC(7)08KH12 Freescale Semiconductor Rev. 1.1 —...

  • Page 73: Interrupt Processing

    MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor FROM RESET BREAK INTERRUPT? I BIT SET? I BIT SET? IRQ1 INTERRUPT? INTERRUPT? OTHER INTERRUPTS? LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION INSTRUCITON? INSTRUCITON? Figure 7-8. Interrupt Processing STACK CPU REGISTERS SET I BIT UNSTACK CPU REGISTERS.

  • Page 74: Hardware Interrupts

    SP – 2 SP – 1 PC – 1[7:0] PC – 1[15:8] OPCODE Figure 7-10. Interrupt Recovery Figure VECT H VECT L START ADDR V DATA H V DATA L OPCODE PC + 1 OPERAND MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 75: Interrupt Recognition Example

    If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor #$FF INT1 PSHH PULH INT2...

  • Page 76: Swi Instruction

    EOF2IE EOPF EOPIE TRANF TRANIE TXDF TXDIE RXDF RXDIE TXD0F TXD0IE RXD0F RXD0IE TXD1F TXD1IE CH0F CH0IE CH1F CH1IE TOIE KEYEF IMASKE Vector Address Priority $FFFC–$FFFD $FFFA–$FFFB $FFF8–$FFF9 $FFF6–$FFF7 $FFF4–$FFF5 $FFF2–$FFF3 $FFF0–$FFF1 $FFEE–$FFEF $FFEC–$FFED MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 77: Interrupt Status Register 1

    Reset: 6–I These flags indicate the presence of interrupt requests from the sources shown in Bit 0 and Bit 1 — Always read 0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Table 7-3. Interrupt Sources Flag Mask KEYDF IMASKD KEYFF IMASKF...

  • Page 78: Interrupt Status Register 2

    IF11 = Reserved Figure 7-13. Interrupt Status Register 2 (INT2) 7 — Interrupt Flags 11–7 Table 7-3. $FE06 Bit 7 = Reserved Figure 7-14. Interrupt Status Register 2 (INT2) Bit 0 IF10 Bit 0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 79: Reset

    The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor (BREAK).) The SIM puts the CPU into the Advance Information (See...

  • Page 80: Wait Mode

    WAIT ADDR WAIT ADDR + 1 PREVIOUS DATA NEXT OPCODE last instruction. Figure 7-15. Wait Mode Entry Timing Figure 7-17 show the timing for WAIT recovery. SAME SAME SAME SAME MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 81: Stop Mode

    NOTE: External crystal applications should use the full stop recovery time by clearing the SSREC bit. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor $6E0B $6E0C Figure 7-16. Wait Recovery from Interrupt or Break Cycles $6E0B Figure 7-17. Wait Recovery from Internal Reset...
  • Page 82 STOP ADDR + 1 PREVIOUS DATA NEXT OPCODE instruction. Figure 7-18. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + 2 SAME SAME SAME SAME SP – 1 SP – 2 SP – 3 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 83: Sim Registers

    The following code is an example of this. Writing zero to the SBSW bit clears MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Table 7-4. SIM Registers Address Register $FE00...

  • Page 84: Reset Status Register (Rsr)

    ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT/STOP opcode. ; Restore H register. $FE01 Bit 7 ILOP = Unimplemented Figure 7-21. Reset Status Register (RSR) Bit 0 ILAD MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 85: Break Flag Control Register (Bfcr)

    Write: Reset: MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of RSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of RSR COP —...
  • Page 86 MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 87: Section 8. Clock Generator Module (Cgm)

    — Freescale Semiconductor Introduction ........88 Features .

  • Page 88: Introduction

    Choosing a Filter Capacitor......111 Reaction Time Calculation ......111 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 89: Features

    • • Figure 8-1 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor VCO Center-Of-Range Frequuency tuned to 48MHz for Low-Jitter Clock Reference for USB Module Low-Frequency Crystal Operation with Low-Power Operation and High-Output Frequency Resolution Programmable Reference Divider for Even Greater Resolution...
  • Page 90 OSCILLATOR PLL ANALOG AUTOMATIC INTERRUPT MODE CONTROL CONTROL AUTO PLLIE PLLF PRE[1:0] CGMVCLK FREQUENCY DIVIDER CGMPCLK Figure 8-1. CGM Block Diagram CGMXCLK CLOCK CGMOUT SELECT ÷ 2 CIRCUIT CLOCK USBCLK SELECT CIRCUIT 48MHz CGMINT MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 91: Crystal Oscillator Circuit

    8.4.3 PLL Circuits The PLL consists of these circuits: • • • • • • • MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Voltage-controlled oscillator (VCO) Reference divider Frequency prescaler Modulo VCO frequency divider Phase detector Loop filter Lock detector Advance Information...
  • Page 92 8.4.6 Programming the PLL VCLK 8.4.4 Acquisition and Tracking . The circuit determines the mode of the PLL and the lock by a factor RCLK is fed back VCLK Modes. The value of the MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 93: Acquisition And Tracking Modes

    MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency.

  • Page 94: Programming The Pll

    , and is cleared when the VCO frequency is out of LOCK . (See 8.9 Acquisition/Lock Time for more information.) (PCTL).) VCLK × ------------- 48MHz × ------------------- - MC68HC(7)08KH12 8.6.1 PLL and the bus VCLK Rev. 1.1 — Freescale Semiconductor...

  • Page 95: Special Programming Exceptions

    MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor the reference clock divider, R. Frequency errors to the PLL are corrected at a rate of f stability and lock time reduction, this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.

  • Page 96: Base Clock Selector Circuit

    The oscillator configuration uses five components: • Crystal, X • Fixed capacitor, C Advance Information 8.4.8 Base Clock Selector Figure 8-2. Figure 8-2 MC68HC(7)08KH12 Circuit.) shows only the logical Rev. 1.1 — Freescale Semiconductor...
  • Page 97 SIMOSCEN OSC1 can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Tuning capacitor, C (can also be a fixed capacitor) Feedback resistor, R Series resistor, R (optional) ) is included in the diagram to follow strict Pierce...

  • Page 98: I/O Signals

    V carefully for maximum noise immunity and place bypass pin. pin. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 99: Buffered Crystal Clock Output (Cgmvout)

    8.5.11 CGM CPU Interrupt (CGMINT) CGMINT is the interrupt signal generated by the PLL lock detector. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor ) and comes directly from the crystal oscillator circuit. XCLK shows only the logical relation of CGMXCLK to OSC1 and Advance Information...

  • Page 100: Cgm Registers

    PLL reference divider select register (PRDS) (See Reference Divider Select Register Table 8-2 Advance Information 8.6.1 PLL Control Register (PBWC).) (PMSH:PMSL).) is a summary of the CGM registers. 8.6.2 PLL 8.6.3 PLL 8.6.4 PLL (PRDS).) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 101 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Table 8-2. CGM I/O Register Summary Bit 7 Read: PLLF PLLIE...

  • Page 102: Pll Control Register (Pctl)

    Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. Advance Information $003A Bit 7 PLLF PLLIE PLLON = Unimplemented Figure 8-3. PLL Control Register (PCTL) Bit 0 PRE1 PRE2 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 103 Programming the PLLON bit is set. Reset clears these bits. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = PLL on 0 = PLL off Circuit.) Reset clears the BCS bit. 1 = Selects the VCO clocks for the base clock.

  • Page 104: Pll Bandwidth Control Register (Pbwc)

    When the AUTO bit is clear, LOCK reads as Advance Information Table 8-3. PRE[1:0] Programming PRE1 PRE0 $003B Bit 7 LOCK AUTO = Unimplemented Figure 8-4. PLL Bandwidth Control Register (PBWC) Prescaler Multiplier Bit 0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 105: Pll Multiplier Select Registers (Pmsh:pmsl)

    Write: Reset: Address: Read: Write: Reset: MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked 1 = Tracking mode 0 = Acquisition mode $003C PMSH Bit 7 $003D PMSL...

  • Page 106: Pll Reference Divider Select Register (Prds)

    PLL.) MUL[11:0] cannot be written when the $003F Bit 7 = Unimplemented PLL.) RDS[7:0] cannot be written when the 8.4.7 Special Programming 8.4.3 PLL Circuits 8.4.6 Bit 0 RDS3 RDS2 RDS1 RDS0 8.4.3 PLL Circuits 8.4.6 Exceptions.) Reset MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 107: Advance Information

    PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK, or LOCK is lost. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Advance Information...

  • Page 108: Cgm During Break Interrupts

    1 MHz and suffers a –100 kHz noise hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5 percent of the 100-kHz step input. Advance Information 7.8.3 Break Flag Control (BFCR).) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 109: Parametric Influences On Reaction Time

    MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Acquisition time, t , is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, ∆...
  • Page 110 . This frequency is the input to the phase and the R value programmed in the reference divider. XCLK Circuits, 8.4.6 Programming the 8.9.3 Choosing a Filter PLL, and 8.6.4 (PRDS).) Capacitor.) . The MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 111: Choosing A Filter Capacitor

    8.4.4 Acquisition and Tracking MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 8.9.2 Parametric Influences on Reaction , is critical to the stability and reaction time of , choose the voltage potential at which the MCU is Correct selection of filter capacitor, C Filter Capacitor.)
  • Page 112 , of not more than ±100  ------------ -   ----------- -  256t VRDV 8.4.5 Modes.) A certain number of . Therefore, the acquisition LOCK , and the acquisition to lock 8.4.8 Base Clock 8.9.2 Parametric MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 113: Section 9. Universal Serial Bus Module (Usb)

    — Freescale Semiconductor Features ......... 114 Overview.

  • Page 114: Features

    – Signal transition interrupt – Frame timer locked interrupt • HUB repeater and controller function – downstream and upstream connectivity – bus state evaluation – selective reset, suspend and resume – fault condition hardware detection Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 115: Overview

    MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Device Control Endpoint 0 and Interrupt Endpoints 1 and 2 – 8-byte transmit buffer – 8-byte receive buffer Device Interrupt Endpoints 1 and 2 –...

  • Page 116: I/O Register Description Of The Hub Function

    USB hub function and the CPU. These registers are shown Table 9-1 Advance Information REGISTERS 12MHz ENDPOINT 0 - 8/8 (CONTROL) Figure 9-1. USB Block Diagram Table 9-2. USBCLK (FROM CGM) 48MHz D0– D1– D4– 3.3V OUT REGULATOR MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 117 USB SIE Timing Status $0057 Register (SIETSR) USB HUB Address Register $0058 (HADDR) USB HUB Interrupt $0059 Register 0 (HIR0) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Bit 7 Read: PEN1 RST1 LOWSP1 Write: Reset: Read: PEN2 RST2 LOWSP2 Write: Reset:...
  • Page 118 Read: RSEQ SETUP TX1ST Write: TX1STR Read: RESUM0 SUSPND Write: = Unimplemented 0** = Reset by POR only TPSIZ3 TPSIZ2 TPSIZ1 TPSIZ0 PCHG3 PCHG2 PCHG1 PCHG0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0 D0– X = Indeterminate MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 119 $0037 Register 7 (HE0D7) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Table 9-2. HUB Data Register Summary Bit 7 Read: HE0R07 HE0R06 HE0R05 HE0R04 HE0R03 HE0R02 HE0R01 HE0R00 Write: HE0T07 HE0T06 HE0T05 HE0T04 HE0T03 HE0T02 HE0T01 HE0T00 Reset: Read: HE0R17 HE0R16 HE0R15 HE0R14 HE0R13 HE0R12 HE0R11 HE0R10...

  • Page 120: Usb Hub Root Port Control Register (Hrpcr)

    RESUMx control bit. Reset clears this bit. Advance Information $005E Bit 7 RESUM0 SUSPND = Unimplemented Bit 0 D0– X = Indeterminate MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 121: Usb Hub Downstream Port Control Register (Hdp1Cr-Hdp4Cr)

    PID. An enabled port propagates all upstream signaling including full speed and low speed packets. This MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Bit 7 PEN1 LOWSP1 RST1 PEN4...
  • Page 122 To indicate the end of the resume, a low speed EOP signal will be followed when this control bit changes from 1 to 0. Reset clears this bit. 1 = Force downstream port data lines to “K” state 0 = Default Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 123: Usb Sie Timing Interrupt Register (Sietir)

    9.4.3 USB SIE Timing Interrupt Register (SIETIR) Address: Read: Write: Reset: MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = Force downstream port enters the selective suspend mode 0 = Default $0056 Bit 7 SOFF EOF2F EOPF TRANF = Unimplemented Figure 9-4.
  • Page 124 Software must clear this flag by writing a logic 1 to the TRANFR bit in the SIETSR register. Reset clears this bit. Writing to TRANF has no effect. 1 = Signal transition has been detected 0 = Signal transition has not been detected Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 125: Usb Sie Timing Status Register (Sietsr)

    Reset: MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = USB interrupt enabled for Start Of Frame 0 = USB interrupt disabled for Start Of Frame 1 = USB interrupt enabled for the Second End Of Frame Point 0 = USB interrupt disabled for the Second End Of Frame Point...
  • Page 126 Writing a logic 1 to this write only bit will clear the TRANF bit if it is set. Writing a logic 0 to the TRANFR has no effect. Reset clears this bit. Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 127: Usb Hub Address Register (Haddr)

    **USBEN bit can only be cleared by a POR reset. ADD6-ADD0 — USB HUB Function Address These bits specify the address of the HUB function. Reset clears these bits. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor $0058 Bit 7 USBEN ADD6 ADD5 0** = Reset by POR only Figure 9-6.

  • Page 128: Usb Hub Interrupt Register 0 (Hir0)

    1 = Receive on HUB Endpoint 0 has occurred 0 = Receive on HUB Endpoint 0 has not occurred Advance Information $0059 Bit 7 TXDF RXDF = Unimplemented Figure 9-7. USB HUB Interrupt Register 0 (HIR0) Bit 0 TXDIE RXDIE TXDFR RXDFR MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 129: Usb Hub Control Register 0 (Hcr0)

    Reset: MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = USB interrupt enabled for Transmit HUB Endpoint 0 0 = USB interrupt disabled for Transmit HUB Endpoint 0 1 = USB interrupt enabled for Receive HUB Endpoint 0 0 = USB interrupt disabled for Receive HUB Endpoint 0...
  • Page 130 RXDF is set, the USB will respond with a NAK handshake to any HUB Endpoint 0 OUT tokens. Reset clears this bit. 1 = Data is ready to be received 0 = Not ready for data. Respond with NAK Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 131: Usb Hub Endpoint1 Control & Data Register (Hcdr)

    Endpoint1. If this bit is 0, a NAK handshake will be returned for next IN token for HUB Endpoint 1. Reset clears this bit. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor $005C Bit 7 STALL1 PNEW PCHG5 PCHG4 Figure 9-9.

  • Page 132: Usb Hub Status Register (Hsr)

    Port 3 status change detected No status change in Port 4 Port 4 status change detected No status change in embedded device Embedded device status change detected Bit 0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0 X = Indeterminate MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 133 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = DATA1 Token received in last HUB Endpoint 0 Receive 0 = DATA0 Token received in last HUB Endpoint 0 Receive 1 = Last token received for hub endpoint 0 was a SETUP token...

  • Page 134: Usb Hub Endpoint 0 Data Registers

    HE0T04 $0037 HE0R76 HE0R75 HE0R74 HE0T76 HE0T75 HE0T74 X = Indeterminate Table 9-3 Bit 0 HE0R03 HE0R02 HE0R01 HE0R00 HE0T03 HE0T02 HE0T01 HE0T00 ↓ HE0R73 HE0R72 HE0R71 HE0R70 HE0T73 HE0T72 HE0T71 HE0T70 Table 9-4. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 135 Control Register 0 (DCR0) USB Embedded Device $004C Control Register 1 (DCR1) USB Embedded Device $004D Status Register (DSR) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Bit 7 Read: Write: Reset: Read: DEVEN DADD6 DADD5 Write: Reset: Read: TXD0F RXD0F Write:...
  • Page 136 Read: DE0R67 DE0R66 DE0R65 DE0R64 DE0R63 DE0R62 DE0R61 DE0R60 Write: DE0T67 DE0T66 DE0T65 DE0T64 DE0T63 DE0T62 DE0T61 DE0T60 Read: DE0R77 DE0R76 DE0R75 DE0R74 DE0R73 DE0R72 DE0R71 DE0R70 Write: DE0T77 DE0T76 DE0T75 DE0T74 DE0T73 DE0T72 DE0T71 DE0T70 Bit 0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 137 (DE1D6) USB Embedded Device $002F Endpoint 1/2 Data Register 7 (DE1D7) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Read: Write: DE1T07 DE1T06 DE1T05 DE1T04 DE1T03 DE1T02 DE1T01 DE1T00 Reset: Read: Write: DE1T17 DE1T16 DE1T15 DE1T14 DE1T13 DE1T12 DE1T11 DE1T10 Reset: Read:...

  • Page 138: Usb Embedded Device Address Register (Daddr)

    Figure 9-13. USB Embedded Device Interrupt Register 0 (DIR0) Advance Information $0048 Bit 7 DEVEN DADD6 DADD5 DADD4 $0049 Bit 7 TXD0F RXD0F = Unimplemented Bit 0 DADD3 DADD2 DADD1 DADD0 Bit 0 TXD0IE RXD0IE TXD0FR RXD0FR MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 139 Reset clears the RXD0IE bit. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = Transmit on embedded device Endpoint 0 has occurred 0 = Transmit on embedded device Endpoint 0 has not occurred 1 = Receive on embedded device Endpoint 0 has occurred...

  • Page 140: Usb Embedded Device Interrupt Register 1 (Dir1)

    NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing to TXD1F has no effect. Advance Information interrupt request interrupt request $004A Bit 7 TXD1F = Unimplemented Bit 0 TXD1IE TXD1FR MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 141: Usb Embedded Device Control Register 0 (Dcr0)

    MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = Transmit on Endpoint 1 or Endpoint 2 of the embedded device has occurred 0 = Transmit on Endpoint 1 or Endpoint 2 of the embedded device has not occurred...
  • Page 142 Endpoint 0 OUT tokens. Reset clears this bit. 1 = Data is ready to be received 0 = Not ready for data. Respond with NAK Advance Information transmit transmit MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 143: Usb Embedded Device Control Register 1 (Dcr1)

    IN token are satisfied (TXD1F=0, TX1E=1, DSTALL2=0, and ENABLE2=1) except that the ENDADD bit is configured for Endpoint 1, the USB responds with a NAK handshake packet. Reset clears this bit. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor $004C Bit 7 T1SEQ ENDADD TX1E = Unimplemented...

  • Page 144: Usb Embedded Device Status Register (Dsr)

    Address: Read: DRSEQ Write: Reset: Figure 9-17. USB Embedded Device Status Register (DSR) Advance Information Packet Size $004D Bit 7 DSETUP DTX1ST DTX1STR = Unimplemented Bit 0 RP0SIZ3 RPS0IZ2 RP0SIZ1 RP0SIZ0 X = Indeterminate MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 145 OUT or SETUP transaction for embedded device Endpoint 0. These bits are not affected by reset. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = DATA1 Token received in last embedded device Endpoint 0 receive 0 = DATA0 Token received in last embedded device Endpoint 0 receive...

  • Page 146: Usb Embedded Device Control Register 2 (Dcr2)

    USB Host Controller. Reset clears this bit. 1 = Send STALL handshake 0 = Default Advance Information $0047 Bit 7 = Unimplemented an IN token an IN token Bit 0 ENABLE2 ENABLE1 DSTALL2 DSTALL1 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 147: Usb Embedded Device Endpoint 0 Data Registers

    These write only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at embedded device Endpoint 0. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = Send STALL handshake 0 = Default Bit 7 DE0R06 DE0R05...

  • Page 148: Usb Embedded Device Endpoint 1/2 Data Registers

    Endpoints 1 and 2 and depend on proper configuration of the ENDADD bit. Advance Information Bit 7 DE1T06 DE1T05 DE1T04 DE1T76 DE1T75 DE1T74 = Unimplemented (UE0D0-UE0D7) Bit 0 DE1T03 DE1T02 DE1T01 DE1T00 ↓ DE1T73 DE1T72 DE1T71 DE1T70 X = Indeterminate MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 149: Contents

    Rev. 1.1 — Freescale Semiconductor Section 10. Monitor ROM (MON) Introduction ........149 Features .

  • Page 150: Features

    PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pull-up resistor. Advance Information Figure 10-1 shows a sample circuit used to enter monitor MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 151 10µF 10µF DB-25 NOTES: Position A — Bus clock = CGMXCLK ÷ 4 Position B — Bus clock = CGMXCLK ÷ 2 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 10µF 20pF 10µF MC74HC125 Figure 10-1. Monitor Mode Circuit 68HC708 10 kΩ...

  • Page 152: Entering Monitor Mode

    Advance Information shows the pin conditions for entering monitor mode. Table 10-1. Mode Selection Mode Monitor Monitor CGMOUT Frequency CGMXCLK ÷ 2 CGMOUT ÷ 2 CGMXCLK CGMOUT ÷ 2 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 153 Table 10-2 monitor mode. Modes User Monitor 1. If the high voltage (V MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor is a summary of the differences between user mode and Table 10-2. Mode Differences Reset Vector High Enabled $FFFE Disabled $FEFE ) is removed from the IRQ1/V asserts its COP enable output.

  • Page 154: Data Format

    Figure 10-4. Read Transaction Figure 10-3.) NEXT START STOP BIT 5 BIT 6 BIT 7 NEXT START BIT 5 BIT 6 BIT 7 STOP STOP NEXT BIT 5 BIT 6 BIT 7 START ADDR. LOW DATA RESULT MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 155: Break Signal

    • • • • • • MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor MISSING STOP BIT Figure 10-5. Break Transaction READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program) (See Figure 10-5.)
  • Page 156 Data Returned None Opcode Command Sequence SENT TO MONITOR WRITE WRITE ADDR. HIGH ECHO Advance Information ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. HIGH ADDR. LOW ADDR. LOW ADDR. LOW DATA RESULT DATA DATA MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 157 Table 10-6. IWRITE (Indexed Write) Command Description Write to last address accessed + 1 Operand Specifies single data byte Data Returned None Opcode Command Sequence SENT TO MONITOR IWRITE IWRITE ECHO MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor DATA DATA RESULT DATA DATA Advance Information...
  • Page 158 MONITOR READSP READSP ECHO Table 10-8. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode Command Sequence SENT TO MONITOR ECHO Advance Information SP HIGH SP LOW RESULT MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 159: Baud Rate

    1024. If the PTC3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Table 10-9. Monitor Baud Rate Selection Crystal PTC3 Frequency (MHz) 4.9152MHz...
  • Page 160 Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 161: Contents

    Rev. 1.1 — Freescale Semiconductor Section 11. Timer Interface Module (TIM) Introduction ........162 Features .

  • Page 162: Introduction

    – External TIM Clock Input (4-MHz Maximum Frequency) • Free-Running or Modulo Up-Count Operation • Toggle Any Channel Pin on Overflow • TIM Counter Stop and Reset Bits • Modular Architecture Expandable to Eight Channels Advance Information Figure MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 163: Functional Description

    CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor shows the structure of the TIM. The central component of PRESCALER SELECT ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A CH1F MS1A Figure 11-1.
  • Page 164 Bit 0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS0B ELS0A TOV0 CH0MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS1B ELS1A TOV1 CH1MAX MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 165: Tim Counter Prescaler

    TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Read: Bit15 Bit14 Bit13 Write:...

  • Page 166: Unbuffered Output Compare

    Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM Advance Information 11.4.3 Output Compare. The pulses are MC68HC(7)08KH12 Freescale Semiconductor Rev. 1.1 —...

  • Page 167: Pulse Width Modulation (Pwm)

    Program the TIM to set the pin if the state of the PWM pulse is logic zero. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Figure 11-2 shows, the output compare value in the TIM channel Advance Information...

  • Page 168: Unbuffered Pwm Signal Generation

    OVERFLOW PERIOD PULSE WIDTH OUTPUT COMPARE Figure 11-2. PWM Period and Pulse Width (see 11.9.1 TIM Status and Control Register 11.4.4 Pulse Width Modulation OVERFLOW OUTPUT OUTPUT COMPARE COMPARE (TSC)). (PWM). The pulses are MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 169: Buffered Pwm Signal Generation

    PWM function, and TIM channel 1 status and MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse.

  • Page 170: Pwm Initialization

    1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 11-3.) compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 11-3.) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 171: Interrupts

    MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor TIM overflow flag (TOF) — The TOF bit is set when the TIM counter value rolls over to $0000 after matching the value in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests.

  • Page 172: Tim During Break Interrupts

    TIM counter instead of the prescaled internal bus clock. Select the PTE0/TCLK input by writing logic ones to the three prescaler select bits, PS[2:0]. Advance Information (See 7.8.3 Break Flag Control Register (See 11.9.1 TIM Status and Control Register (TSC).) The MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 173: Tim Channel I/O Pins (Pte1/Tch0:Pte2/Tch1)

    The TIM status and control register does the following: • • • MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor ------------------------------------ - bus frequency bus frequency ------------------------------------ - TIM status and control register (TSC) TIM control registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL)
  • Page 174 TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active Advance Information $0010 Bit 7 TOIE TSTOP TRST = Unimplemented Figure 11-3. TIM Status and Control Register (TSC) Bit 0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 175: Tim Counter Registers (Tcnth:tcntl)

    TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = Prescaler and TIM counter cleared 0 = No effect Table 11-2. Prescaler Selection Table 11-2 TIM Clock Source Internal Bus Clock ÷...

  • Page 176: Tim Counter Modulo Registers (Tmodh:tmodl)

    Bit 7 Bit15 Bit14 Bit13 Bit12 $0013 TCNTL Bit 7 Bit7 Bit6 Bit5 Bit4 = Unimplemented Figure 11-4. TIM Counter Registers (TCNTH:TCNTL) Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 177: Tim Channel Status And Control Registers (Tsc0:Tsc1)

    Each of the TIM channel status and control registers does the following: • • • • • • • • MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor $0014 TMODH Bit 7 Bit15 Bit14 Bit13 $0015 TMODL Bit 7 Bit7 Bit6 Bit5...
  • Page 178 0 = Channel x CPU interrupt requests disabled Advance Information $0016 TSC0 Bit 7 CH0F CH0IE MS0B MS0A $0019 TSC1 Bit 7 CH1F CH1IE MS1A = Unimplemented Bit 0 ELS0B ELS0A TOV0 CH0MAX Bit 0 ELS1B ELS1A TOV1 CH1MAX MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 179 E, and pin PTEx/TCHx is available as a general-purpose I/O pin. ELSxB and ELSxA bits. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled Table 11-3. 1 = Unbuffered output compare/PWM operation...
  • Page 180 Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare Toggle Output on Compare Clear Output on Compare Set Output on Compare MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 181: Tim Channel Registers (Tch0H/L-Tch1H/L)

    In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor OVERFLOW OVERFLOW PERIOD OUTPUT COMPARE...
  • Page 182 TCH1L Bit 7 Bit7 Bit6 Bit5 Bit4 Indeterminate after reset Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 183: Contents

    — Freescale Semiconductor Introduction ........184 Port A .

  • Page 184: Introduction

    Write: Read: DDRC4 Write: Bit 0 PTA3 PTA2 PTA1 PTA0 PTB3 PTB2 PTB1 PTB0 PTC3 PTC2 PTC1 PTC0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 185 Data Direction Register F $000B (DDRF) Port E Optical Interface $001C Enable Register (EOIER) Port Option Control $001D Register (POC) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Read: DDRD7 DDRD6 DDRD5 Write: Reset: Read: Write: Reset: Read: PTF7 PTF6 PTF5 Write:...

  • Page 186: Port A

    A pin; a logic zero disables the output buffer. Advance Information $0000 Bit 7 PTA7 PTA6 PTA5 PTA4 Unaffected by reset Figure 12-1. Port A Data Register (PTA) (See 12.9 Port Options.) Bit 0 PTA3 PTA2 PTA1 PTA0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 187 The data latch can always be written, regardless of the state of its data direction bit. the operation of the port A pins. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor $0004 Bit 7 DDRA7 DDRA6 DDRA5 DDRA4 Figure 12-2.

  • Page 188: Port B

    Bit 7 PTB7 PTB6 PTB5 PTB4 Unaffected by reset Figure 12-4. Port B Data Register (PTB) (See 12.9 Port Options.). Accesses to PTA Read Write PTA[7:0] PTA[7:0] PTA[7:0] Bit 0 PTB3 PTB2 PTB1 PTB0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 189: Data Direction Register B (Ddrb)

    Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 12-6 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor $0005 Bit 7 DDRB7 DDRB6 DDRB5 DDRB4 Figure 12-5.

  • Page 190: Port C

    $0002 Bit 7 PTC4 Unaffected by reset = Unimplemented Figure 12-7. Port C Data Register (PTC) Table 12-3 summarizes Accesses to PTB DDRB Read Write PTB[7:0] PTB[7:0] PTB[7:0] Bit 0 PTC3 PTC2 PTC1 PTC0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 191: Data Direction Register C (Ddrc)

    Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 12-9 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor (See 12.9 Port Options.) $0006 Bit 7 DDRC4 = Unimplemented Figure 12-8.

  • Page 192: Port D

    Figure 12-9. Port C I/O Circuit Table 12-4. Port C Pin Functions Accesses to PTC Bit I/O Pin Mode Read/Write Input, Hi-Z DDRC[4:0] Output DDRC[4:0] PTCx Table 12-4 summarizes Accesses to PTC DDRC Read Write PTC[4:0] PTC[4:0] PTC[4:0] MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 193: Port D Data Register (Ptd)

    Writing a logic one to a DDRD bit enables the output buffer for the corresponding port D pin; a logic zero disables the output buffer. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor $0003 Bit 7 PTD7 PTD6 PTD5...
  • Page 194 D I/O logic. READ DDRD ($0007) WRITE DDRD ($0007) DDRDx RESET WRITE PTD ($0003) PTDx READ PTD ($0003) Figure 12-12. Port D I/O Circuit Bit 0 DDRD3 DDRD2 DDRD1 DDRD0 PTDx Table 12-5 summarizes MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 195: Port E

    Read: Write: Reset: Alternate Function: Alternate Function: MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Table 12-5. Port D Pin Functions PTD Bit I/O Pin Mode Input, Hi-Z Output $0008 Bit 7 = Unimplemented Figure 12-13. Port E Data Register (PTE) Accesses to...

  • Page 196: Data Direction Register E (Ddre)

    E pin; a logic zero disables the output buffer. Advance Information (TIM). See Section 11. Timer Interface Module (See 15.5.3.2 Port-E Keyboard Interrupt Register.) See Section 15. Keyboard Interrupt Module See Section 11. Timer (TIM). MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 197 The data latch can always be written, regardless of the state of its data direction bit. the operation of the port E pins. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor $000A Bit 7 DDRE4 = Unimplemented Figure 12-14. Data Direction Register E (DDRE)

  • Page 198: Port-E Optical Interface Enable Register

    Table 12-6. Port E Pin Functions Accesses to DDRE I/O Pin Mode Read/Write Input, Hi-Z DDRE[4:0] Output DDRE[4:0] $001C Bit 7 YREF2 YREF1 YREF0 XREF2 Accesses to PTE Read Write PTE[4:0] PTE[4:0] PTE[4:0] Bit 0 XREF1 XREF0 OIEY OIEX MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 199 PTE0 and PTE1. YREF2–YREF0 — Reference Voltage Selection Y These bits sets the slicing reference voltage for optical interface associated with PTE2 and PTE3. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor PTE0-PTE1 / PTE2-PTE3 XREF[2:0] / YREF[2:0] Reference Voltage (mV) Advance Information...
  • Page 200 YREF2 YREF1 YREF0 XREF2 XREF1 XREF0 OIEY OPTICAL INTERFACE REGISTER ($001C) Figure 12-17. Optical Interface Voltage References Advance Information Y - REFERENCE VOLTAGE SELECTOR X - REFERENCE VOLTAGE SELECTOR OIEX MC68HC(7)08KH12 Y-VREF X-VREF Rev. 1.1 — Freescale Semiconductor...
  • Page 201 PTE0 PTE1 PTE2 PTE3 Figure 12-18. Port E Optical Coupling Interface MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor OUTPUT BUFFER OPTICAL INTERFACE SELECT SELECT OPTICAL INTERFACE OUTPUT BUFFER OUTPUT BUFFER OPTICAL INTERFACE SELECT SELECT OPTICAL INTERFACE OUTPUT BUFFER PTE0 PORT LOGIC...

  • Page 202: Port F

    PTF6 PTF5 PTF4 Unaffected by reset KBF7 KBF6 KBF5 KBF4 Figure 12-19. Port F Data Register (PTF) See Section 15. Keyboard Interrupt (KBI). Bit 0 PTF3 PTF2 PTF1 PTF0 KBF3 KBF2 KBF1 KBF0 Register.) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 203: Data Direction Register F (Ddrf)

    Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from 0 to 1. Figure 12-3 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor $000B Bit 7 DDRF7 DDRF6 DDRF5 DDRF4 Figure 12-20.

  • Page 204: Port Options

    I/O Pin Mode Read/Write Input, Hi-Z DDRF[7:0] Output DDRF[7:0] $001D Bit 7 = Unimplemented Figure 12-22. Port Option Control Register (POC) Table 12-7 summarizes Accesses to PTE Read Write PTF[7:0] PTF[7:0] PTF[7:0] Bit 0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 205 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = When respective port is configured as an output, make port C become current limiting 3 mA source/10 mA sink port pins 0 = Configure port C to become standard I/O port pins...
  • Page 206 Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 207: Section 13. Computer Operating Properly (Cop)

    — Freescale Semiconductor Introduction ........207 Functional Description .

  • Page 208: Functional Description

    6-BIT COP COUNTER CLEAR COP COUNTER Bit 7 Read: Write: Read: Low byte of reset vector Write: Clear COP counter Unaffected by reset = Unimplemented RESET CIRCUIT RESET STATUS REGISTER Bit 0 SSREC COPRS STOP COPD MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 209: I/O Signals

    4 of the SIM counter. Reading the COP control register returns the low byte of the reset vector. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor (RSR)). (COPCTL)) clears the COP counter and clears bits 12 – 2 or 2 – 2 CGMXCLK –...

  • Page 210: Power-On Reset

    (See Advance Information (CONFIG).) Figure 13-2 . Configuration Register $001F Bit 7 = Unimplemented Section 5. Configuration Register (CONFIG).) Figure 13-2. Configuration Register (CONFIG) Figure 13-2 . Configuration Bit 0 SSREC COPRS STOP COPD MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 211: Cop Control Register (Copctl)

    The COP is disabled in monitor mode when V IRQ1/V MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = COP reset cycle is (2 0 = COP reset cycle is (2 1 = COP module disabled 0 = COP module enabled...

  • Page 212: Low-Power Modes

    COP timeout period after entering or exiting stop mode. 13.9 COP Module During Break Mode The COP is disabled during a break interrupt when V on the RST pin. Advance Information is present MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 213: Contents

    Rev. 1.1 — Freescale Semiconductor Section 14. External Interrupt (IRQ) Introduction ........213 Features .

  • Page 214: Functional Description

    The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt Exception Advance Information Figure 14-1 shows the structure of the IRQ module. pin are latched into the IRQ1 latch. An Control.) pin. requests.(See 7.6 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 215: Mc68Hc(7)08Kh12 - Rev

    If the MODE1 bit is set, the IRQ1/V and low-level-sensitive. With MODE1 set, both of the following actions must occur to clear IRQ1: MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor IRQ1 IMASK1 MODE1 Figure 14-1. IRQ Module Block Diagram Bit 7...
  • Page 216 Advance Information pin. A falling edge that pin to logic one — As long as the IRQ1/V pin is at logic zero. A reset will clear the latch pin is falling-edge-sensitive only. MC68HC(7)08KH12 Freescale Semiconductor pin to pin. Rev. 1.1 —...

  • Page 217: Irq Module During Break Interrupts

    Address: Read: Write: Reset: MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor (See Section 7. System Integration Module Shows the state of the IRQ1 flag Clears the IRQ1 latch Masks IRQ1 and interrupt request Controls triggering sensitivity of the IRQ1/V $001E Bit 7 = Unimplemented Figure 14-2.
  • Page 218 This read/write bit controls the triggering sensitivity of the IRQ1/V pin. Reset clears MODE1. 1 = IRQ1/V 0 = IRQ1/V Advance Information interrupt requests on falling edges and low levels interrupt requests on falling edges only MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 219: Contents

    — Freescale Semiconductor Introduction ........220 Features .

  • Page 220: Introduction

    Twenty Keyboard Interrupt Pins with Separate Keyboard Interrupt Enable Bits and three Keyboard Interrupt Masks. • Hysteresis Buffers • Internal Pull-ups. • Programmable Edge-Only or Edge- and Level- Interrupt Sensitivity • Exit from Low-Power Modes Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 221 Port F Keyboard Interrupt $0041 Enable Register (KBFIER) Port F Pull-up Enable $0042 Register (PFPER) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Table 15-1. KBI I/O Register Summary Bit 7 Read: Write: Reset: Read: KBDIE7 KBDIE6 KBDIE5 KBDIE4 KBDIE3 KBDIE2 KBDIE1 Write: Reset: Read:...

  • Page 222: Port-D Keyboard Interrupt Block Diagram

    15.4 Port-D Keyboard Interrupt Block Diagram KBD0 TO PULLUP ENABLE KBDIE0 KBD7 TO PULLUP ENABLE KBDIE7 Figure 15-1. Port-D Keyboard Interrupt Block Diagram INTERNAL BUS VECTOR FETCH DECODER ACKD RESET SYNCHRONIZER KEYBOARD IMASKD INTERRUPT FF MODED KEYDF Port-D Keyboard Interrupt Request...

  • Page 223: Port-D Keyboard Interrupt Functional Description

    • MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low.

  • Page 224: Port-D Keyboard Initialization

    1. Mask keyboard interrupts by setting the IMASKD bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBDIEx bits in the keyboard interrupt enable register. Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 225: Port-D Keyboard Interrupt Registers

    Bits [7:4] — Not used These read-only bits always read as logic 0s. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor to clear any false interrupts. DDRD bits in data direction register D. keyboard interrupt enable register. Flags keyboard interrupt requests. Acknowledges keyboard interrupt requests.

  • Page 226: Port-D Keyboard Interrupt Enable Register

    Address: $000D Read: Write: Reset: Figure 15-3. Port-D Keyboard Interrupt Enable Register (KBDIER) Advance Information Bit 7 KBDIE7 KBDIE6 KBDIE5 KBDIE4 Bit 0 KBDIE3 KBDIE2 KBDIE1 KBDIE0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 227 Reset clears the keyboard interrupt enable register. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = KBDx pin enabled as keyboard interrupt pin 0 = KBDx pin not enabled as keyboard interrupt pin Advance Information...

  • Page 228: Port-E Keyboard Interrupt Block Diagram

    15.5 Port-E Keyboard Interrupt Block Diagram KBE0 KBEIE0 TO PULLUP ENABLE PEPE0 KBE3 KBEIE3 TO PULLUP ENABLE PEPE3 Figure 15-4. Port-E Keyboard Interrupt Block Diagram INTERNAL BUS VECTOR FETCH DECODER ACKE RESET SYNCHRONIZER KEYBOARD IMASKE INTERRUPT FF MODEE KEYEF Port-E Keyboard Interrupt Request...

  • Page 229: Port-E Keyboard Interrupt Functional Description

    • MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low.

  • Page 230: Port-E Keyboard Initialization

    2. Write to DDREx bits to make port pin an input pin. 3. Enable the KBI pins by setting the appropriate KBEIEx bits in the keyboard interrupt enable register. Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 231: Port-E Keyboard Interrupt Registers

    This read-only bit is set when a keyboard interrupt is pending on port-E. Reset clears the KEYEF bit. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor to clear any false interrupts. Flags keyboard interrupt requests. Acknowledges keyboard interrupt requests. Masks keyboard interrupt requests.

  • Page 232: Port-E Keyboard Interrupt Enable Register

    Reset clears these bits. 1 = PEPEx pull-up device enabled. 0 = PEPEx pull-up device disabled. Advance Information Bit 7 PEPE3 PEPE2 PEPE1 PEPE0 Bit 0 KBEIE3 KBEIE2 KBEIE1 KBEIE0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 233 Reset clears the keyboard interrupt enable register. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor 1 = KBEx pin enabled as keyboard interrupt pin 0 = KBEDx pin not enabled as keyboard interrupt pin Advance Information...

  • Page 234: Port-F Keyboard Interrupt Block Diagram

    15.6 Port-F Keyboard Interrupt Block Diagram KBF0 KBFIE0 TO PULLUP ENABLE PFPE0 KBF3 KBFIE7 TO PULLUP ENABLE PFPE7 Figure 15-7. Port-F Keyboard Interrupt Block Diagram INTERNAL BUS VECTOR FETCH DECODER ACKF RESET SYNCHRONIZER KEYBOARD IMASKF INTERRUPT FF MODEF KEYFF Port-F Keyboard Interrupt Request...

  • Page 235: Port-F Keyboard Interrupt Functional Description

    • MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low.

  • Page 236: Port-F Keyboard Initialization

    2. Write to DDRFx bits to make the port pin an input pin. 3. Enable the KBI pins by setting the appropriate KBFIEx bits in the keyboard interrupt enable register. Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 237: Port-F Keyboard Interrupt Registers

    This read-only bit is set when a keyboard interrupt is pending on port-F. Reset clears the KEYFF bit. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor to clear any false interrupts. Flags keyboard interrupt requests. Acknowledges keyboard interrupt requests. Masks keyboard interrupt requests.

  • Page 238: Port-F Keyboard Interrupt Enable Register

    1 = KBFx pin enabled as keyboard interrupt pin 0 = KBFx pin not enabled as keyboard interrupt pin Advance Information Bit 7 KBFIE7 KBFIE6 KBFIE5 KBFIE4 Bit 0 KBFIE3 KBFIE2 KBFIE1 KBFIE0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 239: Port-F Pull-Up Enable Register

    The system integration module (SIM) controls whether the keyboard interrupt latch cam be cleared during the break state. The BCFE bit in MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Bit 7 PFPE7 PFPE6 PFPE5 Figure 15-10. Port F Pull-up Enable Register (PFPER)
  • Page 240 To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKx) in the keyboard status and control register during the break state has no effect. Advance Information MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 241: Contents

    Rev. 1.1 — Freescale Semiconductor Section 16. Break Module (BREAK) Introduction ........241 Features .

  • Page 242: Features

    A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Advance Information Figure 16-1 shows the structure of the break module. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 243 Break Address Register $FE0D (BRKL) Break Status/Control $FE0E Register (BRKSCR) MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] Figure 16-1. Break Module Block Diagram Bit 7 Read:...

  • Page 244: Flag Protection During Break Interrupts

    Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) Advance Information 7.8.3 Break Flag Control Register and see the Break Interrupts subsection for each module.) is present MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 245: Break Status And Control Register (Brkscr)

    The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Bit 7 BRKE BRKA = Unimplemented Figure 16-2. Break Status and Control Register (BRKSCR)

  • Page 246: Low-Power Modes

    Bit 7 Bit15 Bit14 Bit13 Bit12 Bit 7 Bit7 Bit6 Bit5 Bit4 Modes). Clear the SBSW bit by writing logic 7.8 SIM Registers. Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 247: Contents

    — Freescale Semiconductor Introduction ........247 Absolute Maximum Ratings .

  • Page 248: Absolute Maximum Ratings

    . Reliability of operation is enhanced if or V for guaranteed Value Unit –0.3 to +6.0 –0.3 to V +0.3 –0.3 to 14.0 –1 to 4.6 ±25 °C –55 to +150 be constrained to the MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 249: Functional Operating Range

    1. Power dissipation is a function of temperature. 2. K is a constant unique to the device. K can be determined for a known T MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Characteristic Characteristic With this value of K, P and T...

  • Page 250: Dc Electrical Characteristics

    — — — — 0.3 × V — — — — µA — ±10 µA — ±1 µA — — — — — — V/ms 2.0 × V kΩ . Measured with all modules MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 251: Control Timing

    2. No more than 10% duty cycle deviation from 50% 3. Consult crystal vendor data sheet 4. Not Required for high frequency crystals MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Symbol and 70% V Symbol — CGMXCLK — CGMXCLK —...

  • Page 252: Usb Dc Electrical Characteristics

    3. No external current draw besides the USB required external resistors should be connected to the REGOUT pin. Advance Information Symbol Conditions 0V<V <3.3V –10 |(D+)–(D–)| Includes V range of 1.5k to 3.6V of 15k to = 4 mA REGOUT = 0°C to +85°C, unless otherwise noted. Unit µA MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 253: Usb Low Speed Source Electrical Characteristics

    6. Timing differences between the differential data signals. 7. Measured at crossover point of differential data signals. 8. Capacitive loading includes 50pF of tester capacitance. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Conditions Symbol (Notes 1,2,3) Notes 4, 5, 8 = 200pF...

  • Page 254: Usb High Speed Source Electrical Characteristics

    =50pF 12Mbs±0.25% 11.97 DRATE 1.0ms±0.05% 0.9995 FRAME =50pF –3.5 Notes 6, 7 –4.0 TEOPT Note 7 TDEOP Note 7 –2 =50pF –18.5 Notes 6, 7 –9 Note 7 EOPR1 EOPR2 Unit 12.03 1.0005 18.5 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 255: Hub Repeater Electrical Characteristics

    9. The maximum load specification is the maximum effective capacitive load allowed that meets the target HUB VBUS droop of 330mV. MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor (Root port and downstream ports configured as low speed) Conditions Symbol (Notes 1,2,3)

  • Page 256: Usb Signaling Levels

    D+ and D– < V Symbol TIH, TCH, Receive (max) (min) and D+ < V (max) (min) and D– < V (max) followed by a J (max) for ≥ 2.5µs Unit — (1/f ) + 5 — MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 257: Clock Generation Module Characteristics

    Operating voltage Operating temperature Crystal reference frequency VCO center-of-range frequency VCO multiply factor VCO prescale multiplier Reference divider factor VCO operating frequency MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor Symbol f XCLK — — Symbol — RCLK — — VCLK Unit —...

  • Page 258: Acquisition/Lock Time Specifications

    — — — If C chosen correctly — If C chosen correctly — ± 3.6% ± 7.2% ± 0.9% ± 1.8% — — — If C chosen correctly — If C chosen correctly — MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...

  • Page 259: Contents

    Rev. 1.1 — Freescale Semiconductor Section 18. Mechanical Specifications Introduction ........259 Plastic Quad Flat Pack (QFP).

  • Page 260: Plastic Quad Flat Pack (Qfp)

    12.00 REF 0.472 REF 0.130 0.170 0.005 0.007 0.40 BSC 0.016 BSC 0.13 0.30 0.005 0.012 16.20 16.60 0.638 0.654 0.20 REF 0.008 REF — — 16.20 16.60 0.638 0.654 1.10 1.30 0.043 0.051 MC68HC(7)08KH12 Rev. 1.1 — Freescale Semiconductor...
  • Page 262 Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.

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