Freescale Semiconductor MCF54455 Reference Manual page 507

SDRAM Controller (SDRAMC)
21.5.1.6 Load Mode/Extended Mode Register Command (
All SDRAM devices contain mode registers that configure the timing and burst mode for the SDRAM.
These commands access the mode registers that physically reside within the SDRAM devices. During the
or command, SDRAM latches the address and bank buses to load the values into the selected
LMR LEMR
mode register.
The
LMR
Use the following steps to write the mode register and extended mode register:
1. Set the SDCR[MODE_EN] bit.
2. Write the SDMR[BA] bits to select the mode register.
3. Write the desired mode register value to the SDMR[ADDR]. Do not overwrite the SDMR[BA]
values. This step can be performed in the same register write in step 2.
4. Set the SDMR[CMD] bit.
5. For DDR, perform steps 2–4 more than once to write the extended-mode register and the mode
register.
For DDR2, perform step 2–4 four times. The first is for the third extended mode register, second
is for the second extended mode register; third is for the first extended mode register; the last is for
the mode register.
6. Clear the SDCR[MODE_EN] bit.
21.5.1.6.1 Mode Register Definition
Figure 21-9 shows a typical mode register definition. This is the SDRAM's mode register, not the
SDRAMC's mode/extended mode register (SDMR) defined in
Mode Register (SDMR)." Refer to the SDRAM manufacturer's device data sheet to confirm correct
settings.
BA1 BA0
Field 0 0
Field
BA1–BA0 Bank address. These must be zero to select the mode register.
A11–A7 Operating mode.
OP_MODE 00000 Normal Operation
00010 Reset DLL
Else Reserved
A6–A4 CAS latency. Delay in clocks from issuing a
CL the CL settings supported can vary from memory to memory.
21-20
and commands are only used during SDRAM initialization.
LEMR
A11 A10 A9 A8
OP_MODE
Figure 21-9. Typical Mode Register
Table 21-11. Mode Register Field Descriptions
READ
NOTE
Section 21.4.1, "SDRAM Mode/Extended
A7 A6 A5 A4
CL
Description
to valid data out. Check the SDRAM manufacturer's spec because
, )
LMR LEMR
A3 A2 A1 A0
BT BLEN
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