Freescale Semiconductor MCF54455 Reference Manual page 551

PCI Bus Controller
31
Address bits [10:8] identify the target function and bits AD[7:2] select one of the 64 configuration Dwords
within the target function's configuration space. For Type 0 configuration transactions, the target device's
IDSEL pin must be asserted. The upper 21 address lines are commonly IDSELs because they are not used
during the address phase of a type 0 configuration transaction.
For a Type 1 access where the target bus is a subordinate bus to the local PCI bus (bus 0), the configuration
transaction remains initiated on bus 0, but the bit pattern AD[1:0] indicates none of the devices on this bus
are the target of the transaction. Rather, only PCI-to-PCI bridges on the local bus should pay attention to
the transaction because it targets a device on a bus further out in the hierarchy beyond a PCI-to-PCI bridge
that is attached to the local PCI bus (bus 0). Initiating a Type 1 configuration transaction (setting AD[1:0]
to 0b01 during the address phase) accomplishes this. This pattern instructs all functions other than
PCI-to-PCI bridges that the transaction is not for any of them.
AD bus during the address phase of the Type 1 configuration access.
31 24 23
Reserved
During the address phase of a Type 1 configuration access, the information on the AD bus is formatted as:
• PCI_AD[1:0] contains 0b01, identifying this as a Type 1 configuration access.
• PCI_AD[7:2] identifies one of 64 configuration Dwords within the target devices's configuration
space.
• PCI_AD[10:8] identifies one of the eight functions within the target physical device.
• PCI_AD[15:11] identifies one of 32 physical devices. The bridge uses this field to select which
device's IDSEL line to assert.
• PCI_AD[23:16] identifies one of 256 PCI buses in the system.
• PCI_AD[31:24] are reserved and are cleared to zero.
During a Type 1 configuration access, PCI devices ignore the state of their IDSEL inputs; PCI devices only
respond to Type 0 accesses. When any PCI-to-PCI bridge latches a Type 1 configuration access (command
equals
CONFIGURATION READ
must determine whether the bus number field on the AD bus matches the number of its secondary bus or
if the field is within the range of its subordinate buses. If the bus number matches, it should claim and pass
the configuration access onto its secondary bus as a Type 0 configuration access, decoding the device
22-34
Target Configuration Doubleword Number
Reserved
Figure 22-37. Type 0 Configuration Transaction:
Contents of the AD Bus During Address Phase
Doubleword Number in the Device's Configuration Space
16 15
Bus Number Device Number
Figure 22-38. Type 1 Configuration Transaction:
Contents of the AD Bus During Address Phase
or
CONFIGURATION WRITE
11 10 8 7
Function Number Dword Number
Figure 22-38 illustrates the contents of the
11 10 8 7
Function
Dword Number
Number
and AD[1:0] equals 0b01) on its primary side, it
2 1 0
0 0
2 1 0
0 1
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