Command Sequence Diagrams - Freescale Semiconductor MCF54455 Reference Manual

Debug Module
Field
3 Address/Data. Determines whether the register field specifies a data or address register.
A/D 0 Data register.
1 Address register.
2–0 Contains the register number in commands that operate on processor registers. See
Register
34.4.1.3.3 Extension Words as Required
Some commands require extension words for addresses and/or immediate data. Addresses require two
extension words because only absolute long addressing is permitted. Longword accesses are forcibly
longword-aligned and word accesses are forcibly word-aligned. Immediate data can be 1 or 2 words long.
Byte and word data each requires a single extension word, while longword data requires two extension
words.
Operands and addresses are transferred most-significant word first. In the following descriptions of the
BDM command set, the optional set of extension words is defined as address, data, or operand data.
34.4.1.4

Command Sequence Diagrams

The command sequence diagram in
represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system
sends to the debug module; the bottom half indicates the debug module's response to the previous
development system commands. Command and result transactions overlap to minimize latency.
Commands transmitted to the debug module
Command code transmitted during this cycle
READ (LONG)
??? 'NOT READY'
Results from previous command
Responses from the debug module
34-31
Table 34-24. BDM Field Descriptions (continued)
Figure 34-20
High-order 16 bits of memory address
Low-order 16 bits of memory address
MS ADDR LS ADDR
'NOT READY'
XXX NEXT CMD
'ILLEGAL' 'NOT READY'
Data used from this transfer
Sequence taken if illegal command
is received by debug module
Figure 34-20. Command Sequence Diagram
Description
shows serial bus traffic for commands. Each bubble
Non-serial-related
Sequence taken if operation
activity
has not completed
READ
MEMORY
'NOT READY'
LOCATION
MS RESULT
Sequence taken if bus error
occurs on memory access
Table 34-26.
Next
Command
XXX
Code
XXX NEXT CMD
LS RESULT
XXX NEXT CMD
BERR 'NOT READY'
High- and low-order 16 bits of result
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