Memory Map/Register Definition - Freescale Semiconductor MCF54455 Reference Manual

Enhanced Direct Memory Access (eDMA)
• The request is considered spurious and discarded, because the request is removed during arbitration
for next channel selection.
• The channel is selected by arbitration and begins execution.
19.4

Memory Map/Register Definition

The eDMA's programming model is partitioned into two regions: the first region defines a number of
registers providing control functions, while the second region corresponds to the local transfer control
descriptor memory.
Reading reserved bits in a register return the value of zero and writes to reserved bits in a register are
ignored. Reading or writing to a reserved memory location generates a bus error.
Address
0xFC04_4000 eDMA Control Register (EDMA_CR)
0xFC04_4004 eDMA Error Status Register (EDMA_ES)
0xFC04_400E eDMA Enable Request Register (EDMA_ERQ)
0xFC04_4016 eDMA Enable Error Interrupt Register (EDMA_EEI)
0xFC04_4018 eDMA Set Enable Request (EDMA_SERQ)
0xFC04_4019 eDMA Clear Enable Request (EDMA_CERQ)
0xFC04_401A eDMA Set Enable Error Interrupt Register (EDMA_SEEI)
0xFC04_401B eDMA Clear Enable Error Interrupt Register (EDMA_CEEI)
0xFC04_401C eDMA Clear Interrupt Request Register (EDMA_CINT)
0xFC04_401D eDMA Clear Error Register (EDMA_CERR)
0xFC04_401E eDMA Set START Bit Register (EDMA_SSRT)
0xFC04_401F eDMA Clear DONE Status Bit Register (EDMA_CDNE)
0xFC04_4026 eDMA Interrupt Request Register (EDMA_INT)
0xFC04_402E eDMA Error Register (EDMA_ERR)
0xFC04_4100 eDMA Channel n Priority Register (DCHPRIn)
+ hex(n) for n = 0 – 15
0xFC04_5000 Transfer Control Descriptor (TCDn)
+ hex(32n) for n = 0 – 15
19.4.1 eDMA Control Register (EDMA_CR)
The EDMA_CR defines the basic operating configuration of the eDMA. Arbitration can be configured to
use a fixed-priority or a round-robin scheme. In fixed-priority arbitration, the highest priority channel
requesting service is selected to execute. The channel priority registers assign the priorities (see
Section 19.4.15, "eDMA Channel n Priority Registers
channel priorities are ignored, and channels are cycled through without regard to priority.
19-4
Table 19-2. eDMA Controller Memory Map
Register
(DCHPRIn)"). In round-robin arbitration mode, the
Width
Access Reset Value Section/Page
(bits)
32 R/W 0x0000_0000
32 R 0x0000_0000
16 R/W 0x0000
16 R/W 0x0000
8 W 0x00
8 W 0x00
8 W 0x00
8 W 0x00
8 W 0x00
8 W 0x00
8 W 0x00
8 W 0x00
32 R/W 0x0000
32 R/W 0x0000
8 R/W See Section
256 R/W See Section
Freescale Semiconductor
19.4.1/19-4
19.4.2/19-5
19.4.3/19-8
19.4.4/19-9
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