Pci Bus Commands - Freescale Semiconductor MCF54455 Reference Manual

22.4.1.4

PCI Bus Commands

PCI supports a number of different commands. The initiator on the PCI_CBE[3:0] signals during the
address phase of a PCI transaction presents these commands.
PCI Bus
PCI_CBE[3:0]
Command
0000
INTERRUPT
ACKNOWLEDGE
0001
SPECIAL CYCLE
0010 /
I O READ
0011 /
I O WRITE
0100 Reserved
0101 Reserved
0110 -
MEMORY READ
0111 -
MEMORY WRITE
1000 Reserved
1001 Reserved
1010
CONFIGURATION
READ
1011
CONFIGURATION
WRITE
1100
MEMORY READ
MULTIPLE
1101
DUAL ADDRESS
CYCLE
Freescale Semiconductor
Table 22-26. PCI Bus Commands
PCI Controller PCI Controller
Supports as Supports as
Initiator Target
Yes No
Yes No
Yes No
Yes No
No No
No No
Yes Yes
Yes Yes
No No
No No
Yes Yes
Yes Yes
Yes Yes
No No
Definition
The
INTERRUPT ACKNOWLEDGE
addressing an external interrupt controller). Only one
device on the PCI bus should respond to the
command.
ACKNOWLEDGE
The command provides a mechanism to
SPECIAL CYCLE
broadcast select messages to all devices on the PCI bus.
The / command accesses agents mapped into the
I O READ
PCI I/O space.
The / command accesses agents mapped into the
I O WRITE
PCI I/O space.
—
—
The command accesses agents mapped into
MEMORY READ
PCI memory space.
The command accesses agents mapped
MEMORY WRITE
into PCI memory space.
—
—
The command accesses the 256 byte
CONFIGURATION READ
configuration space of a PCI agent.
The command accesses the 256
CONFIGURATION WRITE
byte configuration space of a PCI agent.
For the PCI controller as master, the
command functions the same as the
MULTIPLE
command.
READ
For the PCI controller as target, the
command causes an internal bus burst and can prefetch an
additional three bursts worth of data when addressed to
prefetchable space and when PCITCR1[PID] clears.
Internal bus prefetching only applies to PCI reads in the
address range for BAR1–5.
Cache line wrap implements if internal bus is the
transaction initiator and also wraps.
The command transfers a 64-bit
DUAL ADDRESS CYCLE
address (in two 32-bit address cycles) to 64-bit addressable
devices. This device does not respond to this command.
PCI Bus Controller
command is a read (implicitly
INTERRUPT
MEMORY READ
MEMORY
MEMORY READ MULTIPLE
22-31