Freescale Semiconductor MCF54455 Reference Manual page 535

PCI Bus Controller
22.3.2.4 Target Control 1 Register (PCITCR1)
Address: 0xFC0A_806C (PCITCR1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18
R 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0
Field
31–25 Reserved, must be cleared.
24 Latency rule disable. Applies only when ColdFire processor is target. When set, it prevents the PCI controller
LD from automatically issuing a retry disconnect due to the PCI 16/8 clock rule.Normal operation relies on the LD
bit being cleared.
If used, the bit must be set before the 15th PCI clock for first transfer and before the 7th clock for other transfers.
23–18 Reserved, must be cleared.
17 Prefetch invalidate and disable. User sets this bit to invalidate all target prefetched data in the PCI controller.
PID Software can use this bit to invalidate any stale prefetched data when internal memory has been modified by an
internal resource. If prefetched data is currently transferring as read data to the PCI bus when this bit is set, data
transfers stop and the target interface disconnects the current PCI transaction. If set when prefetch data is
currently transferring from the internal bus, data for the current internal bus is marked invalid.
This bit is sticky and completely disables prefetching from the internal bus for PCI when set. This applies to
MEMORY READ MULTIPLE
for the prefetch buffers to work.
16 Prefetch reads. Controls fetching a line from memory in anticipation of request from the external master. The
P target interface continues to prefetch lines from memory as long as PCI_FRAME asserts and there is space to
store the data in the target read buffer.
Note: This bit only applies to PCI reads in the address range for BAR1–5 (prefetchable memory).
Note: Prefetching performs in response to a PCI memory-read-multiple command even if this bit is cleared.
15–9 Reserved, must be cleared.
8 Write combine disable. Applies only when device is target. When set, it prevents PCI controller from
WCD automatically combining write data to be sent out on the internal bus as a burst. Instead, data transfers as soon
as possible on the internal bus as single-beat transactions.
Note: Better target write performance is achieved when this bit cleared.
7–0 Write combine timer. Contains the timer value, in PCI clocks, used when a partial burst is buffered in the target
WCT write data path and write data stops transfer to local memory from the external PCI device. Every time a
sequential beat of write data stores in the buffer, the counter resets with this value.
If partial burst data is buffered (activating the countdown counter) and this field is reprogrammed to a value less
than the current counter value, the counter jumps down to the new WCT value. This way, software can force the
write buffer to flush data to the internal bus more quickly than when the counter was initialized.
The reset value of the write combine timer is 0x08. All 8 bits are programmable.
22.3.2.5 Initiator Window n Base/Translation Address Register (PCIIWnBTAR)
The following register figure describes the three initiator window base/translation address registers.
22-18
17
0 0 0 0 0 0
LD PID P
0 0 0 0 0 0 0 0
Figure 22-18. PCITCR1 Register
Table 22-14. PCITCR1 Field Descriptions
, as well as
MEMORY READ
16 15 14 13 12 11 10 9
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Description
and commands. This bit must be cleared
MEMORY READ LINE
Access: User read/write
8 7 6 5 4 3 2 1
WCD WCT
0 0 0 0 0 1 0 0
Freescale Semiconductor
0
0