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Field
31–0
PC Breakpoint Address. The address to be compared with the PC as a breakpoint trigger.
Address
Note: PBR0[0] should always be loaded with a 0.
DRc[4:0]: 0x18 (PBR1)
0x1A (PBR2)
0x1B (PBR3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 0 0 0
Field
31–1
PC Breakpoint Address. The 31-bit address to be compared with the PC as a breakpoint trigger.
Address
0
Valid Bit. This bit must be set for the PC breakpoint to occur at the address specified in the Address field.
V
0 PBR is disabled.
1 PBR is enabled.
Figure 34-9
shows PBMR. PBMR is accessible in supervisor mode using the WDEBUG instruction and
via the BDM port using the
DRc[4:0]: 0x09 (PBMR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Field
31–0
PC Breakpoint Mask.
Mask
0 The corresponding PBR0 bit is compared to the appropriate PC bit.
1 The corresponding PBR0 bit is ignored.
34.3.7
PC Breakpoint ASID Control Register (PBAC)
The PBAC register configures the breakpoint qualification for each PC breakpoint register (PBRn). Four
bits are dedicated for each breakpoint register and specify how the ASID is used in PC breakpoint
qualification.
Freescale Semiconductor
Table 34-11. PBR0 Field Descriptions
Figure 34-8. PC Breakpoint Register n (PBRn)
Table 34-12. PBRn Field Descriptions
command. PBMR only masks PBR0.
WDMREG
Figure 34-9. PC Breakpoint Mask Register (PBMR)
Table 34-13. PBMR Field Descriptions
Description
Access: Supervisor write-only
Address
Description
Access: Supervisor write-only
Mask
Description
Debug Module
BDM write-only
8
7
6
5
4
3
2
1
0
V
BDM write-only
8
7
6
5
4
3
2
1
0
34-18
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