Freescale Semiconductor MCF54455 Reference Manual page 167

Cache
6.4.7.2 Data Cache-State Transitions
Using the V and M bits, the data cache supports a line-based protocol allowing individual cache lines to
be invalid, valid, or modified. To maintain coherency with memory, the data cache supports write-through
and copyback modes, specified by the corresponding ACR[CM], or CACR[DDCM] if no ACR matches.
Read or write misses to copyback regions cause the cache controller to read a cache line from memory into
the cache. If available, tag and data from memory update an invalid line in the selected set. The line state
then changes from invalid to valid by setting the V bit for the line. If all lines in the row are already valid
or modified, the pseudo-round-robin replacement algorithm selects one of the four lines and replaces the
tag and data. Before replacement, modified lines are buffered temporarily and later copied back to memory
after the new line has been read from memory.
Figure 6-11 shows the three possible data-cache line states and possible processor-initiated transitions for
memory configured as copyback. Transitions are labeled with a capital letter indicating the previous state
and a number indicating the specific case listed in
CI5—DCINVA
CI6—CPUSHL and
DDPI
CI7—CPUSHL and
CD5—DCINVA
CD6—CPUSHL and DDPI
Figure 6-11. Data Cache Line State Diagram—Copyback Mode
Figure 6-12 shows the two possible states for a cache line in write-through mode.
WI3—CPU write miss
WI5—DCINVA
WI6—CPUSHL and DDPI
WI7—CPUSHL and DDPI
Figure 6-12. Data-Cache Line State Diagram—Write-Through Mode
Table 6-6 describes data-cache line transitions and what accesses cause them.
6-22
Table
CI1—CPU read miss
Invalid
V = 0
CV5—DCINVA
CV6—CPUSHL and
CI3—CPU
write miss
CD7—CPUSHL
and DDPI
Modified
V = 1
M = 1
CD2—CPU read hit
CD3—CPU write miss
CD4—CPU write hit
WI1—CPU read miss
Invalid
V = 0
WV5—DCINVA
WV6—CPUSHL and
6-6.
Valid
V = 1
M = 0
CD1—CPU
read miss
CV3—CPU write miss
CV4—CPU write hit
Valid
V = 1
CV1—CPU read miss
CV2—CPU read hit
CV7—CPUSHL and
WV1—CPU read miss
WV2—CPU read hit
WV3—CPU write miss
WV4—CPU write hit
WV7—CPUSHL and
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