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6.2.1
Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified
As shown in
Table
6-1, a data cache line is always in one of three states: invalid, valid-unmodified (often
referred to as exclusive), or valid-modified. An instruction cache line can be valid or invalid. A valid line
can be explicitly invalidated by executing a CPUSHL instruction.
V
M
0
x
Invalid. Ignored during lookups.
1
0
Valid, unmodified. Cache line has valid data that matches system memory.
1
1
Valid, modified. Cache line contains most recent data, data at system memory location is stale.
6.2.2
The Cache at Start-Up
As
Figure 6-3
(A) shows, after power-up, cache contents are undefined; V and M may be set on some lines
even though the cache may not contain the appropriate data for start up. Because reset and power-up do
not invalidate cache lines automatically, the cache should be cleared explicitly by setting
CACR[DCINVA,ICINVA] before the cache is enabled (B).
After the entire cache is flushed, cacheable entries are loaded first in way 0. If way 0 is occupied, the
cacheable entry is loaded into the same set in way 1, as shown in
in detail in
Section 6.4, "Functional Description."
Freescale Semiconductor
Table 6-1. Valid and Modified Bit Settings
Description
Figure 6-3
(D). This process is described
Cache
6-3
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