Sdram Mode Select Control Register (Mscr_Sdram) - Freescale Semiconductor MCF54455 Reference Manual

Pin Multiplexing and Control
16.3.6

SDRAM Mode Select Control Register (MSCR_SDRAM)

The MSCR_SDRAM register controls the slew rate mode of the dedicated SDRAM pins.
Address: 0xFC0A_4074 (MSCR_SDRAM)
7
R
MSCR_SDDATA
W
Reset: 1
Figure 16-48. SDRAM Mode Select Control Register (MSCR_SDRAM)
Field
7–6 SD_D[31:16] slew rate mode. Controls the strength of the SDRAM upper data pins.
MSCR_ 00 Half strength 1.8V mobile DDR
SDDATA 01 Full strength 1.8V mobile DDR
10 1.8V DDR2 without on-chip termination
11 2.5V DDR1
5–4 SD_DQS[3:2] slew rate mode. Controls the strength of the SDRAM DQS pins.
MSCR_ 00 Half strength 1.8V mobile DDR
SDDQS 01 Full strength 1.8V mobile DDR
10 1.8V DDR2 without on-chip termination
11 2.5V DDR1
3–2 SD_CLK and SD_CLK slew rate mode. Controls the strength of the SDRAM clock pins.
MSCR_ 00 Half strength 1.8V mobile DDR
SDCLK 01 Full strength 1.8V mobile DDR
10 1.8V DDR2 without on-chip termination
11 2.5V DDR1
1–0 SD_A10, SD_CAS, SD_CKE, SD_CS[1:0], SD_DQS[3:2], SD_RAS, SD_WE slew rate mode. Controls the
MSCR_ strength of the SDRAM control pins.
SDCTL 00 Half strength 1.8V mobile DDR
01 Full strength 1.8V mobile DDR
10 1.8V DDR2 without on-chip termination
11 2.5V DDR1
16-38
6 5 4
MSCR_SDDQS
1 1 1
Table 16-23. MSCR_SDRAM Field Descriptions
Description
Access: User read/write
3 2 1
MSCR_SDCLK MSCR_SDCTL
1 1 1
Freescale Semiconductor
0
1