Slave Address Transmission; Data Transfer - Freescale Semiconductor MCF54455 Reference Manual

msb
I2C_SCL
1 2
I2C_SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
A
START
Signal
33.3.2

Slave Address Transmission

The master sends the slave address in the first byte after the START signal (B). After the seven-bit calling
address, it sends the R/W bit (C), which tells the slave data transfer direction (0 equals write transfer, 1
equals read transfer).
Each slave must have a unique address. An I
be master and slave at the same time.
The slave whose address matches that sent by the master pulls I2C_SDA low at the ninth serial clock (D)
to return an acknowledge bit.
33.3.3

Data Transfer

When successful slave addressing is achieved, data transfer can proceed (see E in
byte-by-byte basis in the direction specified by the R/W bit sent by the calling master.
Data can be changed only while I2C_SCL is low and must be held stable while I2C_SCL is high, as
Figure 33-7 shows. I2C_SCL is pulsed once for each data bit, with the msb being sent first. The receiving
device must acknowledge each byte by pulling I2C_SDA low at the ninth clock; therefore, a data byte
transfer takes nine clock pulses. See
I2C_SCL
1 2
I2C_SDA
Bit7 Bit6
START
Signal
Freescale Semiconductor
Interrupt bit set
(Byte complete)
lsb
3 4 5 6 7 8
Calling Address
R/W
B
C
2
Figure 33-7. I C Standard Communication Protocol
2
C master must not transmit its own slave address; it cannot
Figure 33-8.
I2C_
Interrupt is serviced
3 4 5 6 7 8
Bit0
Bit5 Bit4 Bit3 Bit2 Bit1
R/W
Slave Address
ACK from
Figure 33-8. Data Transfer
I2C_
SCL held low while
Interrupt is serviced
msb
9 1 2 3
XXX D7 D6 D5
ACK
E
Bit
D
SCL held low while
9 1 2 3 4
Interrupt Bit Set
(Byte Complete)
Bit7 Bit6 Bit5 Bit4
Data Byte
Receiver
2
I C Interface
lsb
4 5 6 7 8 9
D4 D3 D2 D1 D0
Data Byte
No
STOP
ACK
Signal
Bit
Figure 33-7) on a
5 6 7 8 9
Bit3 Bit2 Bit1 Bit0
No
ACK Bit
F
STOP
Signal
33-8