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Chapter 13
Reset Controller Module
13.1
Introduction
The reset controller determines the cause of reset, asserts the appropriate reset signals to the system, and
keeps a history of what caused the reset.
13.1.1
Block Diagram
Figure 13-1
illustrates the reset controller and is explained in these:
13.1.2
Features
Module features include the following:
•
Five sources of reset:
— External
— Power-on reset (POR)
— Core watchdog timer
— Phase locked-loop (PLL) loss of lock
— Software
•
Software-assertable RSTOUT pin independent of chip-reset state
•
Software-readable status flags indicating the cause of the last reset
Freescale Semiconductor
RESET
Pin
Power-On
Reset
Core Watchdog
Controller
Timer Timeout
PLL
Loss of Lock
Software
Reset
Figure 13-1. Reset Controller Block Diagram
RSTOUT
Reset
Pin
To Internal Resets
13-1
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