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Debug Module
The four-bit field correspond directly to the PBRn registers and are functionally identical. They enable or
disable ASID, supervisor mode, and user mode breakpoint qualification. Reset clears these fields,
disabling qualifications, and defaulting to the revision C debug module functionality.
DRc[4:0]: 0x0A (PBAC)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 34-10. PC Breakpoint ASID Control Register (PBAC)
Field
31–16
Reserved, must be cleared.
15–12
PBRn ASID control. Corresponds to the ASID control associated with PBRn. Determines whether the ASID is
PBR3AC
included in the PC breakpoint comparison and whether the operating mode (supervisor or user) is included in the
11–8
comparison logic.
PBR2AC
7–4
PBRnAC[3]
PBR1AC
Not Used
3–0
PBR0AC
x
x
x
x
x
x
34.3.8
Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1)
The ABLR, ABLR1, ABHR and ABHR1 define regions in the processor's data address space that can act
as part of the trigger. These register values are compared with the address for each transfer on the
processor's high-speed local bus. The trigger definition register (TDR) identifies the trigger as one of three
cases:
•
Identically the value in ABLR
•
Inside the range bound by ABLR and ABHR inclusive
•
Outside that same range
XTDR determines the same for ABLR1 and ABHR1.
34-19
Table 34-14. PBAC Field Descriptions
PBRnAC[2]
PBRnAC[1]
ASID
Mode
Included
Qualification
0
0
0
1
0
1
1
0
1
1
1
1
Access: Supervisor read/write
PBR3AC
PBR2AC
Description
PBRnAC[0]
User or
Supervisor
x
No ASID nor mode qualification
0
No ASID qualification; user mode qualification
enabled
1
No ASID qualification; supervisor mode
qualification enabled
x
ASID qualification enabled; no mode qualification
0
ASID and user mode qualification enabled
1
ASID and supervisor mode qualification enabled
BDM read/write
8
7
6
5
4
3
2
1
0
PBR1AC
PBR0AC
Description
Freescale Semiconductor
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