Freescale Semiconductor MCF54455 Reference Manual page 114

Caches are addressed with the virtual address (the cache uses synchronous memory elements), and an
access starts at the rising-clock edge of the first processor local bus pipeline stage. The MMU provides a
physical address midway through this cycle.
If the cache-set address has fewer bits than the in-page address, the cache is considered physically
addressed because these bits are the same in the virtual and physical addresses. If the cache set address has
more bits than the in-page address, one or more of the low-order virtual page number bits are used to
address the cache. The MMU translates these bits; the resulting low-order physical page number bits are
used to determine cache hits.
Address aliasing problems occur when two virtual addresses access one physical page. This is generally
allowed and, if the page is cacheable, one coherent copy of the page image is mapped in the cache at any
time.
If multiple virtual addresses pointing to the same physical address differ only in the low-order virtual page
number bits, conflicting copies can be allocated. For an 8-Kbyte, 4-way, set-associative cache with a
16-byte line size, the cache set address uses address bits 10–4. If virtual addresses 0x0_1000 and 0x0_1400
are mapped to physical address 0x0_1000, using virtual address 0x0_1000 loads cache set 0x00; using
virtual address 0x0_1400 loads cache set 0x40. This puts two copies of the same physical address in the
cache, making this memory space not coherent. To avoid this problem, software must force low-order
virtual page number bits to be equal to low-order physical address bits for all bits used to address the cache
set.
4.3.1.2.6 Supervisor/User Stack Pointers
To isolate supervisor and user modes, the Version 4 ColdFire core implements two A7 register stack
pointers: one for supervisor mode (SSP) and one for user mode (USP). Two former M68000
family-privileged instructions to load and store the user stack pointer are restored in the instruction set
architecture.
4.3.1.2.7 Access Error Stack Frame
Processor local bus accesses that fault (that is, terminate with a transfer error acknowledge) to generate
an access error exception. MMU TLB misses and access violations use the same fault. New fault status
field (FS) encodings in the exception stack frame signal TLB misses on the following to quickly determine
if a fault was due to a TLB miss or another type of access error:
• Instruction fetch
• Instruction extension fetch
• Data read
• Data write
See Section 4.3.3.3, "Access Error Stack Frame
4.3.1.2.8 Expanded Control Register Space
The MMU base-address register (MMUBAR) is added for ColdFire virtual mode. Like other control
registers, it can be accessed from the debug module or written using the privileged MOVEC instruction.
See Section 4.2.2, "MMU Base Address Register
Freescale Semiconductor
Additions," for more information.
(MMUBAR)."
Memory Management Unit (MMU)
4-13