Freescale Semiconductor MPC5200B Manuals

Manuals and User Guides for Freescale Semiconductor MPC5200B. We have 1 Freescale Semiconductor MPC5200B manual available for free PDF download: User Manual

Freescale Semiconductor MPC5200B User Manual (762 pages)

Freescale Semiconductor Board Users Guide

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 4 MB

Mpc5200B Users Guide
1
Table of Contents
2
MPC5200B Users Guide
23
List of Tables
24
External Signals
27
- Features
  27
- Overview
  29
- PSC Functions Overview
  29
- Revision History
  34
Chapter 1 Introduction

36
- Overview
  36
- Features
  36
- Architecture
  37
- Simplified Block Diagram—Mpc5200
  38
- Block Diagram
  38
- Embedded G2_LE Core
  40
- Bestcomm I/O Subsystem
  41
- Programmable Serial Controllers (Pscs)
  41
- 10/100 Ethernet Controller
  41
- Universal Serial Bus (USB)
  41
- Infrared Support
  41
- Inter-Integrated Circuit (I 2 C)
  41
- Serial Peripheral Interface (SPI)
  41
- Byte Data Link Controller - Digital BDLC-D
  42
- System Level Interfaces
  42
- Chip Selects
  42
- Interrupt Controller
  42
- Timers
  42
- General Purpose Input/Outputs (GPIO)
  42
- Functional Pin Multiplexing
  43
- Real-Time Clock (RTC)
  43
- SDRAM Controller and Interface
  43
- Multi-Function External Localplus Bus
  43
- Power Management
  43
- Systems Debug and Test
  44
- Physical Characteristics
  44
Chapter 2 Signal Descriptions

46
- Overview
  46
- Pin PBGA Pin Detail
  47
- Pin PBGA — Top View
  48
- Pinout Tables
  49
  - PSC1 Port Map—5 Pins
    76
  - PSC2 Port Map—5 Pins
    79
  - PSC3 Port Map—10 Pins
    82
  - USB Port Map—10 Pins
    88
  - Ethernet Output Port Map—8 Pins
    91
  - Ethernet Input / Control Port Map—10 Pins
    92
  - Timer Port Map—8 Pins
    107
  - PSC6 Port Map—4 Pins
    110
Chapter 3 Memory Map

120
- Overview
  120
- Internal Register Memory Map
  121
- MPC5200 Memory Map
  122
- MPC5200 Internal Register Space
  122
- External Busses
  122
- SDRAM Bus
  122
- Localplus Bus
  123
- Memory Map Space Register Description
  124
- Memory Address Base Register -MBAR + 0X0000
  124
- Boot and Chip Select Addresses
  124
- SDRAM Chip Select Configuration Registers
  125
- IPBI Control Register and Wait State Enable -Mbar+0X0054
  127
Chapter 4 Resets and Reset Configuration

128
- Overview
  128
- Hard and Soft Reset Pins
  128
- Power-On Reset-PORESET
  128
  - Hard Reset—Hreset
    128
  - Soft Reset—Sreset
    129
- Reset Operation
  129
- Reset Sequence
  129
- Other Resets
  130
- Internal Hard Reset Vs External HRESET Assertion
  130
  - Reset Configuration
    131
Chapter 5 Clocks and Power Management

134
- Clock Distribution Module (CDM)
  134
- Overview
  134
- Primary Synchronous Clock Domains
  135
- MPC5200 Clock Relations
  136
  - Processor Bus (XLB ) Clock Domain
    140
  - SDRAM Memory Controller Clock Domain
    140
  - IPB Clock Domain
    141
  - PCI Clock Domain
    141
    
    Timing Diagram—Clock Waveforms for SDRAM and DDR Memories
    141
    
    Power Management
    142
  - Full-Power Mode
    142
  - Power Conservation Modes
    142
    
    Dynamic Power Mode
    143
    
    Doze Mode
    143
    
    Nap Mode
    143
    
    Sleep Mode
    143
  - Deep-Sleep Mode
    143
    
    Entering Deep Sleep
    144
    
    Exiting Deep Sleep
    144
    
    CDM Registers
    144
    
    CDM JTAG ID Number Register—Mbar + 0X0200
    145
    
    CDM Power on Reset Configuration Register—Mbar + 0X0204
    145
    
    CDM Bread Crumb Register—Mbar + 0X0208
    147
    
    CDM Configuration Register—Mbar + 0X020C
    147
    
    CDM 48Mhz Fractional Divider Configuration Register—Mbar + 0X0210
    148
    
    CDM Clock Enable Register—Mbar + 0X0214
    149
    
    CDM System Oscillator Configuration Register—Mbar + 0X0218
    150
    
    CDM Clock Control Sequencer Configuration Register—Mbar + 0X021C
    151
    
    Psc1 Mclock Config Register—Mbar + 0X
    154
    
    PSC2 Mclock Config Register—Mbar + 0X022C
    155
    
    Psc3 Mclock Config Register—Mbar + 0X
    155
    
    Overview
    158
Chapter 6 G2_LE Processor Core

159
- Not Supported Instruction
  159
- Not Supported XLB Parity Feature
  159
  - Interrupt Controller
    161
  - Machine Check Pin—Core_Mcp
    161
  - System Management Interrupt—Core_Smi
    161
  - Standard Interrupt—Core_Int
    161
Chapter 7 System Integration Unit (SIU)

163
Chapter 8 SDRAM Memory Controller

234
- Terminology and Notation
  234
- Endian"-Ness
  234
  - Features
    239
  - Block Diagram—Sdram Subsystem Example
    247
  - External Signals (SDRAM Side)
    248
  - Functional Description
    248
- Block Diagram
  249
  - Transfer Size
    249
  - Block Diagram—Sdram Memory Controller
    249
  - Commands
    250
    
    Load Mode/Extended Mode Register Command
    250
    
    Precharge All Banks Command
    251
    
    Bank Active Command
    251
    
    Read Command
    251
    
    Write Command
    251
    
    Auto Refresh Command
    252
    
    Self Refresh and Power down Commands
    252
- Operation
  252
  - Power-Up Initialization
    252
  - Read Clock
    253
- Programming the SDRAM Controller
  253
- Memory Controller Registers (Mbar+0X0100:0X010C)
  255
- Address Bus Mapping
  263
  - Example—Physical Address Multiplexing
    264
  - Overview
    266
  - Features
    266
Chapter 9 Localplus Bus (External Bus Interface)

267
- Interface
  267
- External Signals
  267
- LPC Concept Diagram
  268
  - Non-Muxed Mode
    269
- Muxed Mode Address Latching
  269
- Output Enable Signal
  269
  - Muxed Mode
    271
    
    Timing Diagram—Non-Muxed Mode
    271
    
    Address Tenure
    272
    
    Data Tenure
    273
  - Configuration
    274
  - Boot Configuration
    274
- Timing Diagram - Muxed Mode
  274
  - Chip Selects Configuration
    275
  - Reset Configuration
    275
- DMA (Bestcomm) Interface (SCLPC)
  276
- Programmer's Model
  276
- PCI External Signals
  299
Chapter 10 PCI Controller

300
- PCI_AD[31:0] - Address/Data Bus
  300
- PCI_DEVSEL - Device Select
  300
- PCI_FRAME - Frame
  300
- PCI_IDSEL - Initialization Device Select
  300
- PCI_IRDY - Initiator Ready
  300
- Pci Controller Type 0 Configuration Space
  303
- Registers
  304
- PCI Bus Protocol
  342
  - PCI Bus Background
    342
  - Basic Transfer Control
    342
  - PCI Transactions
    343
- PCI Read Terminated by Master
  343
  - PCI Bus Commands
    344
- PCI Write Terminated by Target
  344
  - Addressing
    345
  - Memory Space Addressing
    345
  - Configuration Space Addressing and Transactions
    346
  - I/O Space Addressing
    346
  - Address Decoding
    347
- Contents of the AD Bus During Address Phase of a Type 0 Configuration Transaction
  347
- Contents of the AD Bus During Address Phase of a Type 1 Configuration Transaction
  347
- Initiator Arbitration
  348
  - Priority Scheme
    348
  - Configuration Interface
    348
- XL Bus Initiator Interface
  348
- Initiator Arbitration Block Diagram
  348
  - Endian Translation
    349
  - Configuration Mechanism
    351
- Type 0 Configuration Translation
  351
  - Type 0 Configuration Translation
    352
  - Interrupt Acknowledge Transactions
    353
  - Special Cycle Transactions
    353
  - Type 1 Configuration Translation
    353
  - Transaction Termination
    354
- XL Bus Target Interface
  354
  - Reads from Local Memory
    355
  - Local Memory Writes
    355
    
    Data Translation
    355
  - Target Abort
    356
  - Latrule Disable
    356
- Communication Sub-System Initiator Interface
  356
  - Access Width
    357
    
    Addressing
    357
    
    Data Translation
    357
    
    Initialization
    357
    
    Restart and Reset
    358
    
    PCI Commands
    358
    
    FIFO Considerations
    358
    
    Alarms
    359
    
    Bus Errors
    359
  - PCI - Supported Clock Ratios
    359
  - Interrupts
    359
    
    PCI Bus Interrupts
    359
    
    Internal Interrupt
    359
- PCI Arbiter
  359
- Application Information
  360
  - XL Bus Initiated Transaction Mapping
    360
  - Address Maps
    361
    
    Address Translation
    361
    
    Inbound Address Translation
    361
    
    Outbound Address Translation
    362
- Inbound Address Map
  362
  - Base Address Register Overview
    363
- Outbound Address Map
  363
  - XL Bus Arbitration Priority
    364
- Bestcomm Key Features
  366
- Overview
  366
Chapter 11 ATA Controller

366
- Bestcomm Read
  366
- ATA Controller Interface
  366
  - Bestcomm Write
    367
- ATA Register Interface
  367
- ATA Host Controller Operation
  385
  - PIO State Machine
    386
  - DMA State Machine
    387
    
    Software Requirements
    387
- Signals and Connections
  388
- ATA Interface Description
  389
- Connections—Controller Cable, System Board, MPC5200
  389
- ATA Bus Background
  391
  - Terminology
    391
  - Pin Description—Ata Interface
    391
  - ATA Modes
    392
  - ATA Addressing
    392
    
    ATA Register Addressing
    393
    
    Drive Interrupt
    393
    
    Sector Addressing
    393
    
    Physical/Logical Addressing Modes
    394
- ATA Sector Format
  394
  - ATA Transactions
    395
    
    PIO Mode Transactions
    395
    
    Class 1—PIO Read
    395
    
    Class 2—PIO Write
    396
    
    Timing Diagram—Pio Read Command (Class 1)
    396
    
    Class 3—Non-Data Command
    397
    
    DMA Protocol
    397
    
    Timing Diagram—Pio Write Command (Class 2)
    397
    
    Timing Diagram—Non-Data Command (Class 3)
    397
    
    Flow Diagram—Dma Command Protocol
    399
    
    Multiword DMA Transactions
    400
    
    Class 4—DMA Command
    400
    
    Ultra DMA Protocol
    400
    
    Timing Diagram—Dma Command (Class 4)
    400
- ATA Reset/Power-Up
  401
  - Hardware Reset
    401
  - Software Reset
    401
- ATA I/O Cable Specifications
  402
- Timing Diagram—Reset Timing
  402
Chapter 12 Universal Serial Bus (USB)

404
Chapter 13 Bestcomm

435
- Features Summary
  435
- Descriptors
  436
- Tasks
  436
- Task Descriptor Table
  461
- Variable Table
  461
- Context Save Area
  461
- On-Chip SRAM
  461
- Programming Model
  461
- Task Table
  461
  - Integer Mode
    462
  - Pack
    462
  - Variable Table
    462
    
    Integer Mode
    463
    
    Overview
    466
    
    Block Diagram—Fec
    467
    
    Features
    467
Chapter 14 Fast Ethernet Controller (FEC)

468
Chapter 20 Byte Data Link Controller (BDLC)

468
- Modes of Operation
  468
Chapter 16 XLB Arbiter

588
- Prioritization
  588
- Block Diagram of XLB Arbiter
  588
Chapter 21 Debug Support and JTAG Interface

588
- Overview
  588
Chapter 19 Motorola Scalable CAN (MSCAN)

602
- Features
  602
- SPI Signal Description
  603
- Modes of Operation
  603
Chapter 17 Serial Peripheral Interface (SPI )

603
- Master In/Slave out (MISO)
  603
- Master Out/Slave in (MOSI)
  603
- Serial Clock (SCK)
  603
- Slave Mode
  610
  - Transmission Formats
    610
  - Clock Phase and Polarity Controls
    611
  - Special Features
    614
  - Error Conditions
    615
  - Spi Interrupts
    616
  - Overview
    618
Chapter 18 Inter-Integrated Circuit (IC)

618
- Features
  618
- START Signal
  619
- STOP Signal
  619
  - Slave Address Transmission
    620
  - Data Transfer
    620
  - Acknowledge
    620
    
    Timing Diagram—Start, Address Transfer and Stop Signal
    620
    
    Timing Diagram—Data Transfer
    620
    
    Timing Diagram—Receiver
    621
  - Repeated Start
    621
  - Clock Synchronization and Arbitration
    621
  - Timing Diagram—Receiver Acknowledgement
    621
- Data Transfer, Combined Format
  621
  - Timing Diagram—Clock Synchronization
    622
  - Timing Diagram—Arbitration Procedure
    622
  - System Clock
    624
- Transfer Initiation and Interrupt
  636
  - RXCAN — CAN Receiver Input Pin
    641
  - TXCAN — CAN Transmitter Output Pin
    641
- CAN System
  642
- Memory Map / Register Definition
  643
- Programmer's Model of Message Storage
  661
- User Model for Message Buffer Organization
  666
  - Transmit Structures
    667
  - Receive Structures
    667
  - Identifier Acceptance Filter
    668
- Bit Maskable Identifier Acceptance Filter
  669
- Bit Maskable Identifier Acceptance Filters
  669
  - Protocol Violation Protection
    670
- Bit Maskable Identifier Acceptance Filters
  670
  - Clock System
    671
- MSCAN Clocking Scheme
  671
- Segments Within the Bit Time
  672
  - Timer Link
    673
    
    Listen-Only Mode
    673
    
    Modes of Operation
    673
    
    Normal Modes
    673
  - Low Power Options
    673
    
    CPU Run Mode
    674
    
    CPU Sleep Mode
    674
    
    CPU Deep Sleep Mode
    674
    
    MSCAN Sleep Mode
    674
- Sleep Request / Acknowledge Cycle
  674
  - MSCAN Initialization Mode
    675
- Simplified State Transitions for Entering/Leaving Sleep Mode
  675
  - MSCAN Power down Mode
    676
  - Programmable Wake-Up Function
    676
  - Description of Interrupt Operation
    676
- Initialization Request/Acknowledge Cycle
  676
  - Transmit Interrupt
    677
  - Receive Interrupt
    677
  - Wake-Up Interrupt
    677
  - Error Interrupt
    678
  - Interrupt Acknowledge
    678
  - Recovery from STOP or WAIT
    678
    
    Overview
    680
    
    Features
    680
    
    Modes of Operation
    680
- BDLC Operating Modes State Diagram
  681
- BDLC Block Diagram
  683
- Signal Description
  684
  - BDLC Control Register 1 (DLCBCR1)—MBAR + 0X1300
    684
  - Detailed Signal Descriptions
    684
  - Memory Map and Registers
    684
  - Module Memory Map
    684
  - Overview
    684
  - Register Descriptions
    684
  - RXB - BDLC Receive Pin
    684
  - TXB - BDLC Transmit Pin
    684
  - BDLC State Vector Register (DLCBSVR) - MBAR + 0X1300
    686
  - BDLC Control Register 2 (DLCBCR2) - MBAR + 0X1304
    687
- Types of In-Frame Response
  689
- Functional Description
  695
  - J1850 Frame Format
    695
- J1850 Bus Message Format (VPW)
  695
- J1850 VPW Symbols
  696
  - J1850 VPW Symbols
    697
  - J1850 VPW Valid/Invalid Bits & Symbols
    698
- J1850 VPW Passive Symbols
  701
- J1850 VPW EOF and IFS Symbols
  702
- J1850 VPW Active Symbols
  703
- J1850 VPW BREAK Symbol
  703
- J1850 VPW Bitwise Arbitrations
  704
  - J1850 Bus Errors
    705
  - Mux Interface
    706
    
    Mux Interface - Rx Digital Filter
    706
  - Protocol Handler
    707
- BDLC Module Rx Digital Filter Block Diagram
  707
  - Protocol Architecture
    708
- BDLC Protocol Handler Outline
  708
  - Transmitting a Message
    709
    
    BDLC Transmission Control Bits
    709
    
    Transmitting Exceptions
    710
    
    Aborting a Transmission
    711
  - Receiving a Message
    712
- Basic BDLC Transmit Flowchart
  712
  - BDLC Reception Control Bits
    713
  - Receiving a Message with the BDLC Module
    713
  - Filtering Received Messages
    713
  - Receiving Exceptions
    713
  - Transmitting an In-Frame Response (IFR)
    715
- Basic BDLC Receive Flowchart
  715
  - IFR Types Supported by the BDLC Module
    716
  - BDLC IFR Transmit Control Bits
    716
  - Transmit Single Byte IFR
    717
  - Transmit Multi-Byte IFR 1
    717
  - Transmit Multi-Byte IFR 0
    717
  - Transmitting an IFR with the BDLC Module
    717
- Transmitting a Type 1 IFR
  719
- Transmitting a Type 2 IFR
  720
  - Transmitting IFR Exceptions
    721
  - Receiving an In-Frame Response (IFR)
    722
- Transmitting a Type 3 IFR
  722
- Receiving an IFR with the BDLC Module
  724
- Basic BDLC Module Transmit Flowchart
  726
- Resets
  729
- General
  729
- Basic BDLC Module Initialization Flowchart
  729
- TAP Link Module (TLM) and Slave TAP Implementation
  730
- Overview
  730
- Generic TLM/TAP Architecture Diagram
  731
- Generic TAP Link Module (TLM) Diagram
  732
- TLM and TAP Signal Descriptions
  733
  - Test Reset (TRST)
    733
  - Test Clock (TCK)
    733
  - Test Mode Select (TMS)
    733
  - Test Data in (TDI)
    733
- Generic Slave TAP
  733
  - Test Data out (TDO)
    734
- Slave Test Reset (STRST)
  734
  - Enable Slave—Ena[0:N]
    734
  - Select DR Link—Sel[0:N]
    734
  - Slave Test Data Out—Stdo[0:N]
    734
- TAP State Machines
  734
- State Diagram—Tap Controller
  735
- TLM Link DR Instructions
  736
  - Tlm:tlmena
    737
  - Tlm:ppcena
    737
- TLM Test Instructions
  737
  - Idcode
    737
    
    Device ID Register
    737
  - Bypass
    737
  - Sample/Preload
    737
  - Extest
    738
  - Clamp
    738
  - Highz
    738
  - Interrupt and Bus Errors
    753
  - PCI Controller Type 0 Configuration Space
    754
    
    General Control/Status Registers
    754
    
    Target Control Register PCITCR(RW) —MBAR + 0X0D6C
    754
    
    PCI Arbiter Register PCIARB(RW) —MBAR + 0X0D8C
    754
  - Communication Sub-System Interface Registers
    754
  - I 2 C Status Register (MSR)—MBAR + 0X3D0C
    759

Freescale Semiconductor Categories

Motherboard Computer Hardware Microcontrollers Control Unit Controller

More Freescale Semiconductor Manuals

Freescale Semiconductor MPC5200B Manuals

Freescale Semiconductor MPC5200B User Manual (762 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Signal Descriptions

Chapter 3 Memory Map

Chapter 4 Resets and Reset Configuration

Chapter 5 Clocks and Power Management

Chapter 6 G2_LE Processor Core

Chapter 7 System Integration Unit (SIU)

Chapter 8 SDRAM Memory Controller

Chapter 9 Localplus Bus (External Bus Interface)

Chapter 10 PCI Controller

Chapter 11 ATA Controller

Chapter 12 Universal Serial Bus (USB)

Chapter 13 Bestcomm

Chapter 14 Fast Ethernet Controller (FEC)

Chapter 20 Byte Data Link Controller (BDLC)

Chapter 16 XLB Arbiter

Chapter 21 Debug Support and JTAG Interface

Chapter 19 Motorola Scalable CAN (MSCAN)

Chapter 17 Serial Peripheral Interface (SPI )

Chapter 18 Inter-Integrated Circuit (IC)

Related Products

Freescale Semiconductor Categories