Freescale Semiconductor MCF54455 Reference Manual page 771

DMA Serial Peripheral Interface (DSPI)
Address: 0xFC05_C034 (DSPI_PUSHR)
31 30 29
R
CONT CTAS
W
Reset 0 0 0
15 14 13
R
W
Reset 0 0 0
Figure 31-7. DSPI Push Transmit FIFO Register (DSPI_PUSHR)
Field
31 Continuous peripheral chip select enable. Selects a continuous selection format. The bit is used in SPI master mode.
CONT The bit enables the selected PCS signals to remain asserted between transfers. See
Selection Format," for more information.
0 Return DSPI_PCSn signals to their inactive state between transfers
1 Keep DSPI_PCSn signals asserted between transfers
30–28 Clock and transfer attributes select. Selects which of the DSPI_CTARn registers is used to set the transfer attributes
CTAS for the associated SPI frame. This field is used only in SPI master mode. In SPI slave mode, DSPI_CTAR0 is used
instead.
000 DSPI_CTAR0
001 DSPI_CTAR1
010 DSPI_CTAR2
011 DSPI_CTAR3
100 DSPI_CTAR4
101 DSPI_CTAR5
110 DSPI_CTAR6
111 DSPI_CTAR7
27 End of queue. Provides a means for host software to signal to the DSPI that the current SPI transfer is the last in a
EOQ queue. At the end of the transfer the DSPI_SR[EOQF] bit is set. This bit is used only in SPI master mode.
0 The SPI data is not the last data to transfer
1 The SPI data is the last data to transfer
26 Clear SPI_TCNT. Provides a means for host software to clear the SPI transfer counter. The CTCNT bit clears the
CTCNT DSPI_TCR[SPI_TCNT] field. The SPI_TCNT field is cleared before transmission of the current SPI frame begins.
This bit is used only in SPI master mode.
0 Do not clear DSPI_TCR[SPI_TCNT] field
1 Clear DSPI_TCR[SPI_TCNT] field
25–24 Reserved, must be cleared.
31-18
28 27 26 25
0
CT
EOQ
CNT
0 0 0 0
12 11 10 9
0 0 0 0
Table 31-8. DSPI_PUSHR Field Descriptions
Description
24 23 22 21
0
PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0
0 0 0 0
8 7 6 5
TXDATA
0 0 0 0
Access: User Read/Write
20 19 18 17
0 0 0 0
4 3 2 1
0 0 0 0
Section 31.4.4.5, "Continuous
Freescale Semiconductor
16
0
0
0