Freescale Semiconductor MCF54455 Reference Manual page 82

The index into the exception table is calculated as (4  vector number). After the exception vector
has been fetched, the vector contents determine the address of the first instruction of the desired
handler. After the instruction fetch for the first opcode of the handler has initiated, exception
processing terminates and normal instruction processing continues in the handler.
All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see
Table 3-5).
The table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are
device-specific peripheral interrupt vectors. See
the device-specific interrupt sources.
Vector
Number(s)
0
1
2
3
4
5
6–7
8
9
10
11
12
13
14
15
16–23
24
25–31
32–47
48–60
61
62–63
64–255
1
Fault refers to the PC of the instruction that caused the exception. Next refers to the PC
of the instruction that follows the instruction that caused the fault.
Freescale Semiconductor
Chapter 17, "Interrupt Controller Modules"
Table 3-5. Exception Vector Assignments
Stacked
Vector
Program
Offset (Hex)
Counter
0x000 —
0x004 —
0x008 Fault
0x00C Fault
0x010 Fault
0x014 Fault
0x018–0x01C —
0x020 Fault
0x024 Next
0x028 Fault
0x02C Fault
0x030 Next
0x034 Next
0x038 Fault
0x03C Next
0x040–0x05C —
0x060 Next
0x064–0x07C Next
0x080–0x0BC Next
0x0C0–0x0F0 —
0x0F4 Fault
0x0F8–0x0FC —
0x100–0x3FC Next
Assignment
Initial supervisor stack pointer
Initial program counter
Access error
Address error
Illegal instruction
Divide by zero
Reserved
Privilege violation
Trace
Unimplemented line-A opcode
Unimplemented line-F opcode
Non-PC breakpoint debug interrupt
PC breakpoint debug interrupt
Format error
Uninitialized interrupt
Reserved
Spurious interrupt
Level 1–7 autovectored interrupts
Trap # 0-15 instructions
Reserved
Unsupported instruction
Reserved
Device-specific interrupts
ColdFire Core
for details on
3-16