Introduction - Freescale Semiconductor MCF54455 Reference Manual

Chapter 26
Fast Ethernet Controllers (FEC0 and FEC1)
26.1

Introduction

This chapter provides a -set overview, a functional block diagram, and transceiver connection information
for the 10 and 100 Mbps MII (media independent interface), as well as the low pin-count 10/100 Mbps
reduced MII and 7-wire serial interface. Additionally, detailed descriptions of operation and the
programming model are included.
26.1.1 Overview
The Ethernet media access controller (MAC) supports 10 and 100 Mbps Ethernet/IEEE 802.3 networks.
An external transceiver interface and transceiver function are required to complete the interface to the
media. The FECs support five different standard MAC-PHY (physical) interfaces for connection to an
external Ethernet transceiver. The FECs support the 10/100 Mbps MII, 10/100 Mbps reduced MII, and the
10 Mbps-only 7-wire interface.
The pin multiplexing and control module must be configured to enable the
peripheral function of the appropriate pins (refer to
Multiplexing and
Freescale Semiconductor
NOTE
Control") prior to configuring the FECs.
Chapter 16, "Pin
26-1